Lines Matching +full:0 +full:x1c0

23 #define DP83865_PHY_ID	0x20005c7a
25 #define DP83865_INT_STATUS 0x14
26 #define DP83865_INT_MASK 0x15
27 #define DP83865_INT_CLEAR 0x17
29 #define DP83865_INT_REMOTE_FAULT 0x0008
30 #define DP83865_INT_ANE_COMPLETED 0x0010
31 #define DP83865_INT_LINK_CHANGE 0xe000
37 #define NS_EXP_MEM_CTL 0x16
38 #define NS_EXP_MEM_DATA 0x1d
39 #define NS_EXP_MEM_ADD 0x1e
41 #define LED_CTRL_REG 0x13
42 #define AN_FALLBACK_AN 0x0001
43 #define AN_FALLBACK_CRC 0x0002
44 #define AN_FALLBACK_IE 0x0004
48 hdx_loopback_on = 0,
67 if (ret < 0) in ns_ack_interrupt()
71 * to the corresponding bit in INT_CLEAR (2:0 are reserved) in ns_ack_interrupt()
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
83 if (irq_status < 0) { in ns_handle_interrupt()
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); in ns_handle_interrupt()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
130 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
140 ns_exp_write(phydev, 0x1c0, in ns_10_base_t_hdx_loopack()
141 ns_exp_read(phydev, 0x1c0) | lb_dis); in ns_10_base_t_hdx_loopack()
143 ns_exp_write(phydev, 0x1c0, in ns_10_base_t_hdx_loopack()
144 ns_exp_read(phydev, 0x1c0) & ~lb_dis); in ns_10_base_t_hdx_loopack()
147 (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on"); in ns_10_base_t_hdx_loopack()
162 .phy_id_mask = 0xfffffff0,
177 { DP83865_PHY_ID, 0xfffffff0 },