707 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)  in phy_base_write()  function
734 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_read()
744 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_read()
754 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_read()
776 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_read()
787 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_write()
797 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_write()
801 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);  in vsc85xx_csr_write()
804 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));  in vsc85xx_csr_write()
813 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_write()
829 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_write()
838 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);  in vsc8584_csr_write()
839 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));  in vsc8584_csr_write()
840 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));  in vsc8584_csr_write()
849 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_cmd()
852 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);  in vsc8584_cmd()
861 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_cmd()
878 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_deassert_reset()
890 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_micro_deassert_reset()
896 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);  in vsc8584_micro_deassert_reset()
898 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);  in vsc8584_micro_deassert_reset()
900 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_deassert_reset()
915 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_assert_reset()
920 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
922 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
923 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
927 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
929 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);  in vsc8584_micro_assert_reset()
933 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);  in vsc8584_micro_assert_reset()
935 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |  in vsc8584_micro_assert_reset()
941 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
943 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_assert_reset()
954 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
956 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);  in vsc8584_get_fw_crc()
957 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);  in vsc8584_get_fw_crc()
964 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
969 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_get_fw_crc()
987 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_patch_fw()
993 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |  in vsc8584_patch_fw()
996 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |  in vsc8584_patch_fw()
998 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);  in vsc8584_patch_fw()
1001 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |  in vsc8584_patch_fw()
1005 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_patch_fw()
1007 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_patch_fw()
1018 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_is_serdes_init()
1048 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_is_serdes_init()
1127 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1132 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1134 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8574_config_pre_init()
1141 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);  in vsc8574_config_pre_init()
1143 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1145 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);  in vsc8574_config_pre_init()
1146 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);  in vsc8574_config_pre_init()
1147 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);  in vsc8574_config_pre_init()
1148 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);  in vsc8574_config_pre_init()
1152 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1154 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1159 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8574_config_pre_init()
1161 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8574_config_pre_init()
1163 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1168 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1172 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1174 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1179 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1218 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1221 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);  in vsc8574_config_pre_init()
1222 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);  in vsc8574_config_pre_init()
1223 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,  in vsc8574_config_pre_init()
1242 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1249 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1386 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1391 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1393 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8584_config_pre_init()
1397 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);  in vsc8584_config_pre_init()
1404 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);  in vsc8584_config_pre_init()
1406 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);  in vsc8584_config_pre_init()
1408 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1410 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);  in vsc8584_config_pre_init()
1414 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1416 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1418 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));  in vsc8584_config_pre_init()
1423 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);  in vsc8584_config_pre_init()
1425 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));  in vsc8584_config_pre_init()
1430 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8584_config_pre_init()
1432 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8584_config_pre_init()
1434 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1439 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1443 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1445 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1450 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1491 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);  in vsc8584_config_pre_init()
1493 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);  in vsc8584_config_pre_init()
1498 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);  in vsc8584_config_pre_init()
1504 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_config_pre_init()
1511 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1579 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_host_serdes()
1595 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8584_config_host_serdes()
1599 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_host_serdes()
1644 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_host_serdes()
1662 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8574_config_host_serdes()
1666 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_host_serdes()
1915 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_host_serdes()
1923 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8514_config_host_serdes()
1927 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_host_serdes()
1957 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);  in vsc8514_config_host_serdes()
2003 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
2008 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
2010 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
2014 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
2016 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8514_config_pre_init()
2021 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
2025 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
2027 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
2031 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
2042 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_pre_init()
2046 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);  in vsc8514_config_pre_init()
2051 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);  in vsc8514_config_pre_init()
2056 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8514_config_pre_init()