Lines Matching full:phydev
113 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
115 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
118 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
120 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
123 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
125 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
133 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
135 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
146 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
148 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
151 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
162 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
165 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
172 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
175 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
182 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
183 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
186 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
187 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
192 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
196 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
205 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
210 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
220 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
231 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
237 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
240 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
244 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
258 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
264 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
271 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
276 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
279 const u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
286 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
288 return phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
349 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
358 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
362 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
366 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
367 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
368 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
377 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
381 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
385 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
407 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
411 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
412 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
423 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
431 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
436 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
444 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
447 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
456 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
466 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
470 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
471 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
474 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
479 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
485 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
486 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
506 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
510 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
513 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
525 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, in vsc85xx_update_rgmii_cntl() argument
532 struct device *dev = &phydev->mdio.dev; in vsc85xx_update_rgmii_cntl()
548 if (phy_interface_is_rgmii(phydev)) in vsc85xx_update_rgmii_cntl()
551 rx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, in vsc85xx_update_rgmii_cntl()
554 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in vsc85xx_update_rgmii_cntl()
555 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
561 tx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, in vsc85xx_update_rgmii_cntl()
564 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in vsc85xx_update_rgmii_cntl()
565 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
575 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_update_rgmii_cntl()
581 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
583 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
585 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL, in vsc85xx_default_config()
590 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
595 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
601 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
607 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
614 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
616 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
617 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
618 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
621 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
633 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
638 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
642 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
646 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
651 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
652 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
657 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
660 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
661 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
666 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
691 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
692 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
697 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
700 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
701 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
706 /* phydev->bus->mdio_lock should be locked when using this function */
707 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
714 return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); in phy_base_write()
717 /* phydev->bus->mdio_lock should be locked when using this function */
718 int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
720 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
721 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
725 return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); in phy_base_read()
728 u32 vsc85xx_csr_read(struct phy_device *phydev, in vsc85xx_csr_read() argument
734 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_read()
744 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_read()
754 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_read()
763 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_read()
771 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_read()
774 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_read()
776 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_read()
782 int vsc85xx_csr_write(struct phy_device *phydev, in vsc85xx_csr_write() argument
787 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_write()
797 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_write()
801 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_write()
804 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_write()
813 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_write()
822 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_write()
829 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_write()
836 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
838 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
839 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
840 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
844 int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
849 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
852 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
856 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
861 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
873 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
878 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
890 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
896 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
898 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
906 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
911 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
915 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
918 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
920 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
922 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
923 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
925 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
927 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
929 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
931 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
933 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
935 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
939 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
941 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
943 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
949 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
954 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
956 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
957 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
960 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
964 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
966 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
969 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
975 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
980 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
982 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
987 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
993 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
996 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
998 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
1001 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
1005 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
1007 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
1013 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
1018 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
1021 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
1027 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1033 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
1039 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
1048 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
1054 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
1120 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1127 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1130 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1132 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1134 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1141 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1145 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1146 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1147 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1148 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1150 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1152 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1154 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1157 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1159 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1161 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1163 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1166 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1168 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1170 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1172 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1174 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1177 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1179 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1189 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1196 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1199 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1212 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1218 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1221 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1222 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1223 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1226 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1231 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1242 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1245 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1249 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1257 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, in vsc8584_pll5g_cfg2_wr() argument
1262 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in vsc8584_pll5g_cfg2_wr()
1265 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); in vsc8584_pll5g_cfg2_wr()
1269 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, in vsc8584_mcb_rd_trig() argument
1275 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_rd_trig()
1281 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_rd_trig()
1285 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, in vsc8584_mcb_wr_trig() argument
1292 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_wr_trig()
1298 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_wr_trig()
1302 static int vsc8584_pll5g_reset(struct phy_device *phydev) in vsc8584_pll5g_reset() argument
1307 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1313 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1316 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1324 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1330 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1333 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1343 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1375 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1380 ret = vsc8584_pll5g_reset(phydev); in vsc8584_config_pre_init()
1386 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1389 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1391 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1393 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1395 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1397 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1404 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1406 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1408 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1410 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1412 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1414 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1416 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1418 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1420 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1423 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1425 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1428 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1430 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1432 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1434 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1437 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1439 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1441 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1443 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1445 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1448 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1450 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1460 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1468 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1473 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1476 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1486 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1491 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO); in vsc8584_config_pre_init()
1493 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); in vsc8584_config_pre_init()
1498 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8584_config_pre_init()
1502 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_config_pre_init()
1504 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_config_pre_init()
1508 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1511 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1518 static void vsc8584_get_base_addr(struct phy_device *phydev) in vsc8584_get_base_addr() argument
1520 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_get_base_addr()
1523 phy_lock_mdio_bus(phydev); in vsc8584_get_base_addr()
1524 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_base_addr()
1526 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_get_base_addr()
1529 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_get_base_addr()
1531 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_base_addr()
1532 phy_unlock_mdio_bus(phydev); in vsc8584_get_base_addr()
1538 vsc8531->ts_base_addr = phydev->mdio.addr; in vsc8584_get_base_addr()
1542 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_get_base_addr()
1548 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_get_base_addr()
1558 static void vsc85xx_coma_mode_release(struct phy_device *phydev) in vsc85xx_coma_mode_release() argument
1567 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO); in vsc85xx_coma_mode_release()
1568 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2, in vsc85xx_coma_mode_release()
1570 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_coma_mode_release()
1573 static int vsc8584_config_host_serdes(struct phy_device *phydev) in vsc8584_config_host_serdes() argument
1575 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_host_serdes()
1579 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_host_serdes()
1584 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_host_serdes()
1586 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8584_config_host_serdes()
1588 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8584_config_host_serdes()
1595 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_host_serdes()
1599 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_host_serdes()
1606 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_host_serdes()
1611 ret = vsc8584_cmd(phydev, val); in vsc8584_config_host_serdes()
1618 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_host_serdes()
1627 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_host_serdes()
1635 return vsc85xx_sd6g_config_v2(phydev); in vsc8584_config_host_serdes()
1638 static int vsc8574_config_host_serdes(struct phy_device *phydev) in vsc8574_config_host_serdes() argument
1640 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8574_config_host_serdes()
1644 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_host_serdes()
1649 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8574_config_host_serdes()
1651 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8574_config_host_serdes()
1653 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8574_config_host_serdes()
1655 } else if (phy_interface_is_rgmii(phydev)) { in vsc8574_config_host_serdes()
1662 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8574_config_host_serdes()
1666 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_host_serdes()
1671 if (!phy_interface_is_rgmii(phydev)) { in vsc8574_config_host_serdes()
1674 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8574_config_host_serdes()
1679 ret = vsc8584_cmd(phydev, val); in vsc8574_config_host_serdes()
1687 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8574_config_host_serdes()
1696 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8574_config_host_serdes()
1703 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1705 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1709 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1711 phy_lock_mdio_bus(phydev); in vsc8584_config_init()
1726 if (phy_package_init_once(phydev)) { in vsc8584_config_init()
1731 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1733 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_config_init()
1738 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1741 ret = vsc8574_config_host_serdes(phydev); in vsc8584_config_init()
1749 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1752 ret = vsc8584_config_host_serdes(phydev); in vsc8584_config_init()
1755 vsc85xx_coma_mode_release(phydev); in vsc8584_config_init()
1766 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1768 ret = vsc8584_macsec_init(phydev); in vsc8584_config_init()
1772 ret = vsc8584_ptp_init(phydev); in vsc8584_config_init()
1776 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1780 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1784 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL, in vsc8584_config_init()
1790 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1795 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1803 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1807 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) in vsc8584_handle_interrupt() argument
1812 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_handle_interrupt()
1819 ret = vsc8584_handle_ts_interrupt(phydev); in vsc8584_handle_interrupt()
1824 vsc8584_handle_macsec_interrupt(phydev); in vsc8584_handle_interrupt()
1827 phy_trigger_machine(phydev); in vsc8584_handle_interrupt()
1832 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1835 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1837 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1841 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1845 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1849 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1852 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1857 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1862 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1870 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1877 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1885 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1899 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1901 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1905 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1907 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1910 static int vsc8514_config_host_serdes(struct phy_device *phydev) in vsc8514_config_host_serdes() argument
1915 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_host_serdes()
1920 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_host_serdes()
1923 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_host_serdes()
1927 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_host_serdes()
1932 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8514_config_host_serdes()
1936 ret = vsc8584_cmd(phydev, in vsc8514_config_host_serdes()
1941 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", in vsc8514_config_host_serdes()
1953 vsc8584_micro_assert_reset(phydev); in vsc8514_config_host_serdes()
1954 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8514_config_host_serdes()
1957 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val); in vsc8514_config_host_serdes()
1959 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_host_serdes()
1961 return vsc85xx_sd6g_config_v2(phydev); in vsc8514_config_host_serdes()
1964 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1992 struct device *dev = &phydev->mdio.dev; in vsc8514_config_pre_init()
1997 ret = vsc8584_pll5g_reset(phydev); in vsc8514_config_pre_init()
2003 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
2006 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
2008 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
2010 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
2012 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
2014 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
2016 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
2019 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
2021 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
2023 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
2025 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
2027 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
2029 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
2031 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
2039 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2041 vsc8584_micro_assert_reset(phydev); in vsc8514_config_pre_init()
2042 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_pre_init()
2046 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); in vsc8514_config_pre_init()
2051 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8514_config_pre_init()
2054 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8514_config_pre_init()
2056 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8514_config_pre_init()
2063 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2067 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2071 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
2073 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
2076 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
2078 phy_lock_mdio_bus(phydev); in vsc8514_config_init()
2091 if (phy_package_init_once(phydev)) { in vsc8514_config_init()
2092 ret = vsc8514_config_pre_init(phydev); in vsc8514_config_init()
2095 ret = vsc8514_config_host_serdes(phydev); in vsc8514_config_init()
2098 vsc85xx_coma_mode_release(phydev); in vsc8514_config_init()
2101 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2103 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
2109 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
2115 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
2123 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2127 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
2131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
2132 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
2137 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
2141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
2142 rc = vsc85xx_ack_interrupt(phydev); in vsc85xx_config_intr()
2146 vsc8584_config_macsec_intr(phydev); in vsc85xx_config_intr()
2147 vsc8584_config_ts_intr(phydev); in vsc85xx_config_intr()
2149 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
2152 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2155 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
2159 rc = vsc85xx_ack_interrupt(phydev); in vsc85xx_config_intr()
2165 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) in vsc85xx_handle_interrupt() argument
2169 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_handle_interrupt()
2171 phy_error(phydev); in vsc85xx_handle_interrupt()
2178 phy_trigger_machine(phydev); in vsc85xx_handle_interrupt()
2183 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
2187 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
2191 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
2194 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
2198 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
2202 return genphy_read_status(phydev); in vsc85xx_read_status()
2205 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
2212 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
2216 phydev->priv = vsc8531; in vsc8514_probe()
2218 vsc8584_get_base_addr(phydev); in vsc8514_probe()
2219 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8514_probe()
2226 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
2231 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2234 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2241 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2245 phydev->priv = vsc8531; in vsc8574_probe()
2247 vsc8584_get_base_addr(phydev); in vsc8574_probe()
2248 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8574_probe()
2255 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2260 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2263 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2271 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2272 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2276 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2280 phydev->priv = vsc8531; in vsc8584_probe()
2282 vsc8584_get_base_addr(phydev); in vsc8584_probe()
2283 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, in vsc8584_probe()
2290 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2295 if (phy_package_probe_once(phydev)) { in vsc8584_probe()
2296 ret = vsc8584_ptp_probe_once(phydev); in vsc8584_probe()
2301 ret = vsc8584_ptp_probe(phydev); in vsc8584_probe()
2305 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2308 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2315 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2319 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2323 phydev->priv = vsc8531; in vsc85xx_probe()
2330 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2335 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()