14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN865X_REVB0 0x0007C1B3
17 #define LAN867X_REG_STS2 0x0019
21 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
22 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
23 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
24 #define LAN865X_REG_STS2 0x0019
30  * RMW 0x1F 0x00D0 0x0002 0x0E03
31  * RMW 0x1F 0x00D1 0x0000 0x0300
32  * RMW 0x1F 0x0084 0x3380 0xFFC0
33  * RMW 0x1F 0x0085 0x0006 0x000F
34  * RMW 0x1F 0x008A 0xC000 0xF800
35  * RMW 0x1F 0x0087 0x801C 0x801C
36  * RMW 0x1F 0x0088 0x033F 0x1FFF
37  * W   0x1F 0x008B 0x0404 ------
38  * RMW 0x1F 0x0080 0x0600 0x0600
39  * RMW 0x1F 0x00F1 0x2400 0x7F00
40  * RMW 0x1F 0x0096 0x2000 0x2000
41  * W   0x1F 0x0099 0x7F80 ------
45 	0x00D0, 0x00D1, 0x0084, 0x0085,
46 	0x008A, 0x0087, 0x0088, 0x008B,
47 	0x0080, 0x00F1, 0x0096, 0x0099,
51 	0x0002, 0x0000, 0x3380, 0x0006,
52 	0xC000, 0x801C, 0x033F, 0x0404,
53 	0x0600, 0x2400, 0x2000, 0x7F80,
57 	0x0E03, 0x0300, 0xFFC0, 0x000F,
58 	0xF800, 0x801C, 0x1FFF, 0xFFFF,
59 	0x0600, 0x7F00, 0x2000, 0xFFFF,
64 	0x0091, 0x0081, 0x0043, 0x0044,
65 	0x0045, 0x0053, 0x0054, 0x0055,
66 	0x0040, 0x0050, 0x00D0, 0x00E9,
67 	0x00F5, 0x00F4, 0x00F8, 0x00F9,
68 	0x00B0, 0x00B1, 0x00B2, 0x00B3,
69 	0x00B4, 0x00B5, 0x00B6, 0x00B7,
70 	0x00B8, 0x00B9, 0x00BA, 0x00BB,
74 	0x9660, 0x00C0, 0x00FF, 0xFFFF,
75 	0x0000, 0x00FF, 0xFFFF, 0x0000,
76 	0x0002, 0x0002, 0x5F21, 0x9E50,
77 	0x1CF8, 0xC020, 0x9B00, 0x4E53,
78 	0x0103, 0x0910, 0x1D26, 0x002A,
79 	0x0103, 0x070D, 0x1720, 0x0027,
80 	0x0509, 0x0E13, 0x1C25, 0x002B,
84 	0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF
89  * write_register(0x4, 0x00D8, addr)
90  * write_register(0x4, 0x00DA, 0x2)
91  * return (int8)(read_register(0x4, 0x00D9))
93  * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2
117 	const u16 fixup_regs[2] = {0x0004, 0x0008};  in lan865x_generate_cfg_offsets()
120 	for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {  in lan865x_generate_cfg_offsets()
122 		if (ret < 0)  in lan865x_generate_cfg_offsets()
125 			offsets[i] = ret | 0xE0;  in lan865x_generate_cfg_offsets()
130 	return 0;  in lan865x_generate_cfg_offsets()
137 	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {  in lan865x_read_cfg_params()
140 		if (ret < 0)  in lan865x_read_cfg_params()
145 	return 0;  in lan865x_read_cfg_params()
152 	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {  in lan865x_write_cfg_params()
160 	return 0;  in lan865x_write_cfg_params()
178 	cfg_results[0] = (cfg_params[0] & 0x000F) |  in lan865x_setup_cfgparam()
179 			  FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |  in lan865x_setup_cfgparam()
180 			  FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]);  in lan865x_setup_cfgparam()
181 	cfg_results[1] = (cfg_params[1] & 0x03FF) |  in lan865x_setup_cfgparam()
183 	cfg_results[2] = (cfg_params[2] & 0xC0C0) |  in lan865x_setup_cfgparam()
184 			  FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) |  in lan865x_setup_cfgparam()
185 			  (9 + offsets[0]);  in lan865x_setup_cfgparam()
186 	cfg_results[3] = (cfg_params[3] & 0xC0C0) |  in lan865x_setup_cfgparam()
187 			  FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) |  in lan865x_setup_cfgparam()
188 			  (14 + offsets[0]);  in lan865x_setup_cfgparam()
189 	cfg_results[4] = (cfg_params[4] & 0xC0C0) |  in lan865x_setup_cfgparam()
190 			  FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) |  in lan865x_setup_cfgparam()
191 			  (22 + offsets[0]);  in lan865x_setup_cfgparam()
203 	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) {  in lan865x_revb0_config_init()
211 	 * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760)  in lan865x_revb0_config_init()
224 	if (err < 0)  in lan867x_revb1_config_init()
230 		if (err < 0)  in lan867x_revb1_config_init()
244 	for (int i = 0; i < ARRAY_SIZE(lan867x_revb1_fixup_registers); i++) {  in lan867x_revb1_config_init()
253 	return 0;  in lan867x_revb1_config_init()
268 	return 0;  in lan86xx_read_status()