57 #define	PHYACC_ATTR_BANK_DSP		4  macro
297 	if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {  in lan937x_dsp_workaround()
459 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
461 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
463 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
465 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
467 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
469 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
475 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
478 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
480 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
483 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
485 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
487 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
490 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
493 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
495 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
497 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
499 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
501 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
503 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
505 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
507 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
509 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
511 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
513 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
515 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
517 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
519 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
521 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
523 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
525 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
527 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
529 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
531 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
533 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
535 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
537 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
539 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
541 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
543 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
545 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
547 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
549 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
551 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
553 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
555 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
557 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
559 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
561 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
563 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
566 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
569 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
572 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
575 		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
577 		{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,  in lan87xx_phy_init()
765 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,  in lan87xx_cable_test_start()
768 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,  in lan87xx_cable_test_start()
771 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,  in lan87xx_cable_test_start()
774 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,  in lan87xx_cable_test_start()
777 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,  in lan87xx_cable_test_start()
780 		{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,  in lan87xx_cable_test_start()
783 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,  in lan87xx_cable_test_start()
786 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,  in lan87xx_cable_test_start()
877 			       PHYACC_ATTR_BANK_DSP, 151, 0);  in lan87xx_cable_test_report()
880 			       PHYACC_ATTR_BANK_DSP, 153, 0);  in lan87xx_cable_test_report()
882 			       PHYACC_ATTR_BANK_DSP, 154, 0);  in lan87xx_cable_test_report()
884 				    PHYACC_ATTR_BANK_DSP, 156, 0);  in lan87xx_cable_test_report()
886 				    PHYACC_ATTR_BANK_DSP, 157, 0);  in lan87xx_cable_test_report()
936 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,  in lan87xx_cable_test_get_status()
944 				 PHYACC_ATTR_BANK_DSP,  in lan87xx_cable_test_get_status()
1018 			 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);  in lan87xx_get_sqi()
1023 			 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);  in lan87xx_get_sqi()