Lines Matching +full:0 +full:x9680
11 #define MTK_GPHY_ID_MT7981 0x03a29461
12 #define MTK_GPHY_ID_MT7988 0x03a29481
14 #define MTK_EXT_PAGE_ACCESS 0x1f
15 #define MTK_PHY_PAGE_STANDARD 0x0000
16 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
18 #define MTK_PHY_LPI_REG_14 0x14
19 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
21 #define MTK_PHY_LPI_REG_1c 0x1c
24 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
25 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
28 #define TXRESERVE_MIN 0
31 #define MTK_PHY_ANARG_RG 0x10
35 #define MTK_PHY_TXVLD_DA_RG 0x12
37 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
39 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
41 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
43 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
45 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
47 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
49 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
51 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
53 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
55 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
57 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
59 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
61 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
63 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
65 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
67 #define MTK_PHY_RXADC_CTRL_RG7 0xc6
70 #define MTK_PHY_RXADC_CTRL_RG9 0xc8
74 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
76 #define MTK_PHY_LDO_OUTPUT_V 0xd7
78 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb
81 #define MTK_PHY_RG_ZCALEN_A BIT(0)
83 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc
87 #define MTK_PHY_RG_TXVOS_CALEN BIT(0)
89 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0
92 #define MTK_PHY_RG_TX_FILTER 0xfe
94 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
96 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
98 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
99 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
101 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
104 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
106 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
108 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
110 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
112 #define MTK_PHY_RG_AD_CAL_COMP 0x17a
115 #define MTK_PHY_RG_AD_CAL_CLK 0x17b
116 #define MTK_PHY_DA_CAL_CLK BIT(0)
118 #define MTK_PHY_RG_AD_CALIN 0x17c
119 #define MTK_PHY_DA_CALIN_FLAG BIT(0)
121 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
122 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
124 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
125 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
127 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
128 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
130 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
131 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
133 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
134 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
136 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
137 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
139 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
140 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
142 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
143 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
145 #define MTK_PHY_RG_DEV1E_REG19b 0x19b
148 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
149 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
150 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
151 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
152 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
153 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
154 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230
155 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231
156 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232
157 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233
159 #define MTK_PHY_RG_DEV1E_REG234 0x234
160 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
164 #define MTK_PHY_RG_LPF_CNT_VAL 0x235
166 #define MTK_PHY_RG_DEV1E_REG238 0x238
167 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
170 #define MTK_PHY_RG_DEV1E_REG239 0x239
171 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
174 #define MTK_PHY_RG_DEV1E_REG27C 0x27c
176 #define MTK_PHY_RG_DEV1E_REG27D 0x27d
177 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
179 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
180 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
183 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
184 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
189 #define MTK_PHY_RG_DEV1E_REG323 0x323
190 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
193 #define MTK_PHY_RG_DEV1E_REG324 0x324
194 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
197 #define MTK_PHY_RG_DEV1E_REG326 0x326
198 #define MTK_PHY_LPI_MODE_SD_ON BIT(0)
204 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
205 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
207 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
208 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
209 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
210 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
213 #define MTK_PHY_LED0_ON_CTRL 0x24
214 #define MTK_PHY_LED1_ON_CTRL 0x26
215 #define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
216 #define MTK_PHY_LED_ON_LINK1000 BIT(0)
229 #define MTK_PHY_LED0_BLINK_CTRL 0x25
230 #define MTK_PHY_LED1_BLINK_CTRL 0x27
231 #define MTK_PHY_LED_BLINK_1000TX BIT(0)
250 #define MTK_PHY_RG_BG_RASEL 0x115
251 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
254 #define RG_GPIO_MISC_TPBANK0 0x6f0
258 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
259 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
260 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
261 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
262 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
264 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
265 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
266 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
267 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
268 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
270 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
271 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
273 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
274 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
302 #define MTK_PHY_LED_STATE_FORCE_ON 0
355 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
363 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); in rext_fill_result()
367 return 0; in rext_fill_result()
374 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); in rext_cal_efuse()
378 return 0; in rext_cal_efuse()
384 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); in tx_offset_fill_result()
392 return 0; in tx_offset_fill_result()
399 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); in tx_offset_cal_efuse()
406 return 0; in tx_offset_cal_efuse()
435 for (i = 0; i < 12; i++) { in tx_amp_fill_result()
438 bias[i] = 0; in tx_amp_fill_result()
443 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); in tx_amp_fill_result()
445 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); in tx_amp_fill_result()
447 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); in tx_amp_fill_result()
449 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); in tx_amp_fill_result()
478 return 0; in tx_amp_fill_result()
485 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); in tx_amp_cal_efuse()
486 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); in tx_amp_cal_efuse()
487 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); in tx_amp_cal_efuse()
488 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); in tx_amp_cal_efuse()
491 return 0; in tx_amp_cal_efuse()
497 int bias = 0; in tx_r50_fill_result()
503 val = clamp_val(bias + tx_r50_cal_val, 0, 63); in tx_r50_fill_result()
524 return 0; in tx_r50_fill_result()
550 return 0; in tx_r50_cal_efuse()
632 } else if (ret == 0) { in tx_vcm_cal_sw()
661 if (ret < 0) in tx_vcm_cal_sw()
669 ret = 0; in tx_vcm_cal_sw()
678 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); in tx_vcm_cal_sw()
681 ret = 0; in tx_vcm_cal_sw()
689 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", in tx_vcm_cal_sw()
691 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && in tx_vcm_cal_sw()
692 lower_ret == 0) { in tx_vcm_cal_sw()
693 ret = 0; in tx_vcm_cal_sw()
694 phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", in tx_vcm_cal_sw()
718 __phy_write(phydev, 0x11, 0xc71); in mt798x_phy_common_finetune()
719 __phy_write(phydev, 0x12, 0xc); in mt798x_phy_common_finetune()
720 __phy_write(phydev, 0x10, 0x8fae); in mt798x_phy_common_finetune()
723 __phy_write(phydev, 0x11, 0x2f00); in mt798x_phy_common_finetune()
724 __phy_write(phydev, 0x12, 0xe); in mt798x_phy_common_finetune()
725 __phy_write(phydev, 0x10, 0x8fb0); in mt798x_phy_common_finetune()
728 __phy_write(phydev, 0x11, 0x55a0); in mt798x_phy_common_finetune()
729 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
730 __phy_write(phydev, 0x10, 0x83aa); in mt798x_phy_common_finetune()
733 __phy_write(phydev, 0x11, 0x240); in mt798x_phy_common_finetune()
734 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
735 __phy_write(phydev, 0x10, 0x9680); in mt798x_phy_common_finetune()
737 /* TrFreeze = 0 (mt7988 default) */ in mt798x_phy_common_finetune()
738 __phy_write(phydev, 0x11, 0x0); in mt798x_phy_common_finetune()
739 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
740 __phy_write(phydev, 0x10, 0x9686); in mt798x_phy_common_finetune()
748 __phy_write(phydev, 0x11, 0xbaef); in mt798x_phy_common_finetune()
749 __phy_write(phydev, 0x12, 0x2e); in mt798x_phy_common_finetune()
750 __phy_write(phydev, 0x10, 0x968c); in mt798x_phy_common_finetune()
751 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_common_finetune()
756 u16 val[8] = { 0x01ce, 0x01c1, in mt7981_phy_finetune()
757 0x020f, 0x0202, in mt7981_phy_finetune()
758 0x03d0, 0x03c0, in mt7981_phy_finetune()
759 0x0013, 0x0005 }; in mt7981_phy_finetune()
766 for (k = 0, i = 1; i < 12; i++) { in mt7981_phy_finetune()
767 if (i % 3 == 0) in mt7981_phy_finetune()
774 __phy_write(phydev, 0x11, 0x600); in mt7981_phy_finetune()
775 __phy_write(phydev, 0x12, 0x0); in mt7981_phy_finetune()
776 __phy_write(phydev, 0x10, 0x8fc0); in mt7981_phy_finetune()
779 __phy_write(phydev, 0x11, 0x4c2a); in mt7981_phy_finetune()
780 __phy_write(phydev, 0x12, 0x3e); in mt7981_phy_finetune()
781 __phy_write(phydev, 0x10, 0x8fa4); in mt7981_phy_finetune()
786 __phy_write(phydev, 0x11, 0xd10a); in mt7981_phy_finetune()
787 __phy_write(phydev, 0x12, 0x34); in mt7981_phy_finetune()
788 __phy_write(phydev, 0x10, 0x8f82); in mt7981_phy_finetune()
791 __phy_write(phydev, 0x11, 0x5555); in mt7981_phy_finetune()
792 __phy_write(phydev, 0x12, 0x55); in mt7981_phy_finetune()
793 __phy_write(phydev, 0x10, 0x8ec0); in mt7981_phy_finetune()
794 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7981_phy_finetune()
799 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); in mt7981_phy_finetune()
802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
805 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); in mt7981_phy_finetune()
806 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
807 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); in mt7981_phy_finetune()
808 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
809 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); in mt7981_phy_finetune()
810 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); in mt7981_phy_finetune()
812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); in mt7981_phy_finetune()
813 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); in mt7981_phy_finetune()
814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); in mt7981_phy_finetune()
818 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); in mt7981_phy_finetune()
820 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); in mt7981_phy_finetune()
823 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); in mt7981_phy_finetune()
824 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); in mt7981_phy_finetune()
826 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); in mt7981_phy_finetune()
831 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, in mt7988_phy_finetune()
832 0x020d, 0x0206, 0x0384, 0x03d0, in mt7988_phy_finetune()
833 0x03c6, 0x030a, 0x0011, 0x0005 }; in mt7988_phy_finetune()
837 for (i = 0; i < 12; i++) in mt7988_phy_finetune()
841 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); in mt7988_phy_finetune()
845 __phy_write(phydev, 0x11, 0x500); in mt7988_phy_finetune()
846 __phy_write(phydev, 0x12, 0x0); in mt7988_phy_finetune()
847 __phy_write(phydev, 0x10, 0x8fc0); in mt7988_phy_finetune()
854 __phy_write(phydev, 0x11, 0xb90a); in mt7988_phy_finetune()
855 __phy_write(phydev, 0x12, 0x6f); in mt7988_phy_finetune()
856 __phy_write(phydev, 0x10, 0x8f82); in mt7988_phy_finetune()
859 __phy_write(phydev, 0x11, 0xfbba); in mt7988_phy_finetune()
860 __phy_write(phydev, 0x12, 0xc3); in mt7988_phy_finetune()
861 __phy_write(phydev, 0x10, 0x87f8); in mt7988_phy_finetune()
863 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7988_phy_finetune()
868 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); in mt7988_phy_finetune()
871 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); in mt7988_phy_finetune()
880 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | in mt798x_phy_eee()
881 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); in mt798x_phy_eee()
887 0xff)); in mt798x_phy_eee()
902 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); in mt798x_phy_eee()
911 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | in mt798x_phy_eee()
912 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); in mt798x_phy_eee()
917 0x33) | in mt798x_phy_eee()
927 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | in mt798x_phy_eee()
937 /* Regsigdet_sel_1000 = 0 */ in mt798x_phy_eee()
938 __phy_write(phydev, 0x11, 0xb); in mt798x_phy_eee()
939 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
940 __phy_write(phydev, 0x10, 0x9690); in mt798x_phy_eee()
943 __phy_write(phydev, 0x11, 0x114f); in mt798x_phy_eee()
944 __phy_write(phydev, 0x12, 0x2); in mt798x_phy_eee()
945 __phy_write(phydev, 0x10, 0x969a); in mt798x_phy_eee()
948 __phy_write(phydev, 0x11, 0x3028); in mt798x_phy_eee()
949 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
950 __phy_write(phydev, 0x10, 0x969e); in mt798x_phy_eee()
953 __phy_write(phydev, 0x11, 0x5010); in mt798x_phy_eee()
954 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
955 __phy_write(phydev, 0x10, 0x96a0); in mt798x_phy_eee()
958 __phy_write(phydev, 0x11, 0x24a); in mt798x_phy_eee()
959 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
960 __phy_write(phydev, 0x10, 0x96a8); in mt798x_phy_eee()
963 __phy_write(phydev, 0x11, 0x3210); in mt798x_phy_eee()
964 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
965 __phy_write(phydev, 0x10, 0x96b8); in mt798x_phy_eee()
967 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ in mt798x_phy_eee()
968 __phy_write(phydev, 0x11, 0x1463); in mt798x_phy_eee()
969 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
970 __phy_write(phydev, 0x10, 0x96ca); in mt798x_phy_eee()
973 __phy_write(phydev, 0x11, 0x36); in mt798x_phy_eee()
974 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
975 __phy_write(phydev, 0x10, 0x8f80); in mt798x_phy_eee()
976 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
980 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); in mt798x_phy_eee()
983 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); in mt798x_phy_eee()
984 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
989 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); in mt798x_phy_eee()
1010 return 0; in cal_sw()
1041 return 0; in cal_efuse()
1067 return 0; in start_cal()
1072 int ret = 0; in mt798x_phy_calibration()
1081 return 0; in mt798x_phy_calibration()
1089 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { in mt798x_phy_calibration()
1136 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); in mt798x_phy_hw_led_on_set()
1146 (index ? 16 : 0), &priv->led_state); in mt798x_phy_hw_led_on_set()
1151 on ? MTK_PHY_LED_ON_FORCE_ON : 0); in mt798x_phy_hw_led_on_set()
1153 return 0; in mt798x_phy_hw_led_on_set()
1159 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); in mt798x_phy_hw_led_blink_set()
1169 (index ? 16 : 0), &priv->led_state); in mt798x_phy_hw_led_blink_set()
1173 blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); in mt798x_phy_hw_led_blink_set()
1175 return 0; in mt798x_phy_hw_led_blink_set()
1183 int err = 0; in mt798x_phy_led_blink_set()
1188 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { in mt798x_phy_led_blink_set()
1232 return 0; in mt798x_phy_led_hw_is_supported()
1238 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); in mt798x_phy_led_hw_control_get()
1239 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); in mt798x_phy_led_hw_control_get()
1240 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); in mt798x_phy_led_hw_control_get()
1250 if (on < 0) in mt798x_phy_led_hw_control_get()
1256 if (blink < 0) in mt798x_phy_led_hw_control_get()
1277 return 0; in mt798x_phy_led_hw_control_get()
1303 return 0; in mt798x_phy_led_hw_control_get()
1309 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); in mt798x_phy_led_hw_control_set()
1311 u16 on = 0, blink = 0; in mt798x_phy_led_hw_control_set()
1334 (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) | in mt798x_phy_led_hw_control_set()
1335 ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) | in mt798x_phy_led_hw_control_set()
1336 ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) : in mt798x_phy_led_hw_control_set()
1342 (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) | in mt798x_phy_led_hw_control_set()
1343 ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) | in mt798x_phy_led_hw_control_set()
1344 ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) : in mt798x_phy_led_hw_control_set()
1374 if (led_num == 0) in mt7988_phy_led_get_polarity()
1391 for (index = 0; index < 2; ++index) in mt7988_phy_fix_leds_polarities()
1396 MTK_PHY_LED_ON_POLARITY : 0); in mt7988_phy_fix_leds_polarities()
1403 return 0; in mt7988_phy_fix_leds_polarities()
1437 return 0; in mt7988_phy_probe_shared()
1444 for (i = 0; i < 2; ++i) in mt798x_phy_leds_state_init()
1457 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, in mt7988_phy_probe()
1484 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); in mt7988_phy_probe()