1 // SPDX-License-Identifier: GPL-2.0+
33 /* IP101A/G - IP1001 */
42 #define	IP101A_G_IRQ_PIN_USED		BIT(15) /* INTR pin used */
69 /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
70  * (pin number 21). The hardware default is RXER (receive error) mode. But it
102 		err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);  in ip175c_config_init()
107 		err = mdiobus_read(phydev->mdio.bus, 30, 0);  in ip175c_config_init()
113 		err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);  in ip175c_config_init()
118 		err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);  in ip175c_config_init()
124 			err = mdiobus_write(phydev->mdio.bus, i,  in ip175c_config_init()
131 			err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);  in ip175c_config_init()
138 	if (phydev->mdio.addr != 4) {  in ip175c_config_init()
139 		phydev->state = PHY_RUNNING;  in ip175c_config_init()
140 		phydev->speed = SPEED_100;  in ip175c_config_init()
141 		phydev->duplex = DUPLEX_FULL;  in ip175c_config_init()
142 		phydev->link = 1;  in ip175c_config_init()
143 		netif_carrier_on(phydev->attached_dev);  in ip175c_config_init()
170 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in ip1001_config_init()
172 		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in ip1001_config_init()
174 		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in ip1001_config_init()
187 	if (phydev->mdio.addr == 4) /* WAN port */  in ip175c_read_status()
191 		phydev->irq = PHY_MAC_INTERRUPT;  in ip175c_read_status()
198 	if (phydev->mdio.addr == 4) /* WAN port */  in ip175c_config_aneg()
206 	struct device *dev = &phydev->mdio.dev;  in ip101a_g_probe()
211 		return -ENOMEM;  in ip101a_g_probe()
214 	 * pin on the 32-pin IP101GR, so this is an exclusive choice.  in ip101a_g_probe()
216 	if (device_property_read_bool(dev, "icplus,select-rx-error") &&  in ip101a_g_probe()
217 	    device_property_read_bool(dev, "icplus,select-interrupt")) {  in ip101a_g_probe()
220 		return -EINVAL;  in ip101a_g_probe()
223 	if (device_property_read_bool(dev, "icplus,select-rx-error"))  in ip101a_g_probe()
224 		priv->sel_intr32 = IP101GR_SEL_INTR32_RXER;  in ip101a_g_probe()
225 	else if (device_property_read_bool(dev, "icplus,select-interrupt"))  in ip101a_g_probe()
226 		priv->sel_intr32 = IP101GR_SEL_INTR32_INTR;  in ip101a_g_probe()
228 		priv->sel_intr32 = IP101GR_SEL_INTR32_KEEP;  in ip101a_g_probe()
230 	phydev->priv = priv;  in ip101a_g_probe()
237 	struct ip101a_g_phy_priv *priv = phydev->priv;  in ip101a_g_config_intr_pin()
244 	/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */  in ip101a_g_config_intr_pin()
245 	switch (priv->sel_intr32) {  in ip101a_g_config_intr_pin()
265 		 * For the 32-pin IP101GR we simply keep the SEL_INTR32  in ip101a_g_config_intr_pin()
331 			phydev->mdix_ctrl = ETH_TP_MDI_X;  in ip101a_g_read_status()
333 			phydev->mdix_ctrl = ETH_TP_MDI;  in ip101a_g_read_status()
335 		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;  in ip101a_g_read_status()
339 		phydev->mdix = ETH_TP_MDI_X;  in ip101a_g_read_status()
341 		phydev->mdix = ETH_TP_MDI;  in ip101a_g_read_status()
355 	switch (phydev->mdix_ctrl) {  in ip101a_g_config_mdix()
413 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in ip101a_g_config_intr()
418 		/* INTR pin used: Speed/link/duplex will cause an interrupt */  in ip101a_g_config_intr()
508 	if (phydev->phy_id != IP101A_PHY_ID)  in ip101a_g_match_phy_device()
550 	struct ip101a_g_phy_priv *priv = phydev->priv;  in ip101g_get_stat()
558 		priv->stats[i] += val;  in ip101g_get_stat()
559 		ret = priv->stats[i];  in ip101g_get_stat()
634 MODULE_DEVICE_TABLE(mdio, icplus_tbl);