net/phy/dp83640_reg.h

1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PTP_TSTS                  0x0017 /* PTP Trigger Status Register */
20 #define PTP_TXTS                  0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS                  0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
26 #define PTP_TRIG                  0x0014 /* PTP Trigger Configuration Register */
57 #define TRIG_SEL_SHIFT            (10)    /* PTP Trigger Select */
59 #define TRIG_DIS                  (1<<9)  /* Disable PTP Trigger */
60 #define TRIG_EN                   (1<<8)  /* Enable PTP Trigger */
61 #define TRIG_READ                 (1<<7)  /* Read PTP Trigger */
62 #define TRIG_LOAD                 (1<<6)  /* Load PTP Trigger */
73 #define TRIG_DONE                 (1<<9)  /* PTP Trigger Done */
77 #define TRIG_IE                   (1<<1)  /* Trigger Interrupt Enable */
81 #define TRIG7_ERROR               (1<<15) /* Trigger 7 Error */
82 #define TRIG7_ACTIVE              (1<<14) /* Trigger 7 Active */
83 #define TRIG6_ERROR               (1<<13) /* Trigger 6 Error */
84 #define TRIG6_ACTIVE              (1<<12) /* Trigger 6 Active */
85 #define TRIG5_ERROR               (1<<11) /* Trigger 5 Error */
86 #define TRIG5_ACTIVE              (1<<10) /* Trigger 5 Active */
87 #define TRIG4_ERROR               (1<<9)  /* Trigger 4 Error */
88 #define TRIG4_ACTIVE              (1<<8)  /* Trigger 4 Active */
89 #define TRIG3_ERROR               (1<<7)  /* Trigger 3 Error */
90 #define TRIG3_ACTIVE              (1<<6)  /* Trigger 3 Active */
91 #define TRIG2_ERROR               (1<<5)  /* Trigger 2 Error */
92 #define TRIG2_ACTIVE              (1<<4)  /* Trigger 2 Active */
93 #define TRIG1_ERROR               (1<<3)  /* Trigger 1 Error */
94 #define TRIG1_ACTIVE              (1<<2)  /* Trigger 1 Active */
95 #define TRIG0_ERROR               (1<<1)  /* Trigger 0 Error */
96 #define TRIG0_ACTIVE              (1<<0)  /* Trigger 0 Active */
101 #define PTP_RATE_HI_SHIFT         (0)     /* PTP Rate High 10-bits */
107 #define EVNT_TS_LEN_SHIFT         (6)     /* Indicates length of the Timestamp field in 16-bit word…
136 #define TRIG_IF_LATE              (1<<13) /* trigger immediately if already past */
137 #define TRIG_NOTIFY               (1<<12) /* Trigger Notification Enable */
138 #define TRIG_GPIO_SHIFT           (8)     /* Trigger GPIO Connection, value 1-12 */
140 #define TRIG_TOGGLE               (1<<7)  /* Trigger Toggle Mode Enable */
141 #define TRIG_CSEL_SHIFT           (1)     /* Trigger Configuration Select */
143 #define TRIG_WR                   (1<<0)  /* Trigger Configuration Write */
149 #define EVNT_GPIO_SHIFT           (8)     /* Event GPIO Connection, value 1-12 */
159 #define IGNORE_2STEP              (1<<11) /* Ignore Two_Step flag for One-Step operation */
160 #define CRC_1STEP                 (1<<10) /* Disable checking of CRC for One-Step operation */
161 #define CHK_1STEP                 (1<<9)  /* Enable UDP Checksum correction for One-Step Operation …
162 #define IP1588_EN                 (1<<8)  /* Enable IEEE 1588 defined IP address filter */
177 #define MAC_SRC_ADD_SHIFT         (11)    /* Status Frame Mac Source Address */
187 #define PSF_TRIG_EN               (1<<1)  /* Trigger PHY Status Frame Enable */
193 #define USER_IP_SEL               (1<<13) /* Selects portion of IP address accessible thru PTP_RXCF…
194 #define USER_IP_EN                (1<<12) /* Enable User-programmed IP address filter */
196 #define IP1588_EN_SHIFT           (8)     /* Enable IEEE 1588 defined IP address filters */
212 #define TS_MIN_IFG_SHIFT          (12)    /* Minimum Inter-frame Gap */
235 #define PTP_CLKDIV_SHIFT          (0)     /* PTP Clock Divide-by Value */
249 #define TX_SFD_GPIO_SHIFT         (4)     /* TX SFD GPIO Select, value 1-12 */
251 #define RX_SFD_GPIO_SHIFT         (0)     /* RX SFD GPIO Select, value 1-12 */