Lines Matching +full:ts +full:- +full:attached
1 // SPDX-License-Identifier: GPL-2.0+
145 /* list of the other attached phyters, not chosen */
165 static int chosen_phy = -1;
194 index = gpio_tab[CALIBRATE_GPIO] - 1; in dp83640_gpio_defaults()
198 index = gpio_tab[PEROUT_GPIO] - 1; in dp83640_gpio_defaults()
203 index = gpio_tab[i] - 1; in dp83640_gpio_defaults()
205 pd[index].chan = i - EXTTS0_GPIO; in dp83640_gpio_defaults()
222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); in broadcast_write()
228 struct dp83640_private *dp83640 = phydev->priv; in ext_read()
231 if (dp83640->clock->page != page) { in ext_read()
233 dp83640->clock->page = page; in ext_read()
244 struct dp83640_private *dp83640 = phydev->priv; in ext_write()
246 if (dp83640->clock->page != page) { in ext_write()
248 dp83640->clock->page = page; in ext_write()
258 const struct timespec64 *ts, u16 cmd) in tdr_write() argument
260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ in tdr_write()
261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ in tdr_write()
262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ in tdr_write()
263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ in tdr_write()
276 sec = p->sec_lo; in phy2rxts()
277 sec |= p->sec_hi << 16; in phy2rxts()
279 rxts->ns = p->ns_lo; in phy2rxts()
280 rxts->ns |= (p->ns_hi & 0x3fff) << 16; in phy2rxts()
281 rxts->ns += ((u64)sec) * 1000000000ULL; in phy2rxts()
282 rxts->seqid = p->seqid; in phy2rxts()
283 rxts->msgtype = (p->msgtype >> 12) & 0xf; in phy2rxts()
284 rxts->hash = p->msgtype & 0x0fff; in phy2rxts()
285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in phy2rxts()
293 sec = p->sec_lo; in phy2txts()
294 sec |= p->sec_hi << 16; in phy2txts()
296 ns = p->ns_lo; in phy2txts()
297 ns |= (p->ns_hi & 0x3fff) << 16; in phy2txts()
307 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
308 struct phy_device *phydev = dp83640->phydev; in periodic_output()
313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
316 return -EINVAL; in periodic_output()
331 mutex_lock(&clock->extreg_lock); in periodic_output()
334 mutex_unlock(&clock->extreg_lock); in periodic_output()
338 sec = clkreq->perout.start.sec; in periodic_output()
339 nsec = clkreq->perout.start.nsec; in periodic_output()
340 pwidth = clkreq->perout.period.sec * 1000000000UL; in periodic_output()
341 pwidth += clkreq->perout.period.nsec; in periodic_output()
344 mutex_lock(&clock->extreg_lock); in periodic_output()
368 mutex_unlock(&clock->extreg_lock); in periodic_output()
378 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_adjfine()
385 scaled_ppm = -scaled_ppm; in ptp_dp83640_adjfine()
397 mutex_lock(&clock->extreg_lock); in ptp_dp83640_adjfine()
402 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_adjfine()
411 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_adjtime()
412 struct timespec64 ts; in ptp_dp83640_adjtime() local
417 ts = ns_to_timespec64(delta); in ptp_dp83640_adjtime()
419 mutex_lock(&clock->extreg_lock); in ptp_dp83640_adjtime()
421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); in ptp_dp83640_adjtime()
423 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_adjtime()
429 struct timespec64 *ts) in ptp_dp83640_gettime() argument
433 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_gettime()
436 mutex_lock(&clock->extreg_lock); in ptp_dp83640_gettime()
445 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_gettime()
447 ts->tv_nsec = val[0] | (val[1] << 16); in ptp_dp83640_gettime()
448 ts->tv_sec = val[2] | (val[3] << 16); in ptp_dp83640_gettime()
454 const struct timespec64 *ts) in ptp_dp83640_settime() argument
458 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_settime()
461 mutex_lock(&clock->extreg_lock); in ptp_dp83640_settime()
463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); in ptp_dp83640_settime()
465 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_settime()
475 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_enable()
479 switch (rq->type) { in ptp_dp83640_enable()
482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | in ptp_dp83640_enable()
486 return -EOPNOTSUPP; in ptp_dp83640_enable()
489 if ((rq->extts.flags & PTP_STRICT_FLAGS) && in ptp_dp83640_enable()
490 (rq->extts.flags & PTP_ENABLE_FEATURE) && in ptp_dp83640_enable()
491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) in ptp_dp83640_enable()
492 return -EOPNOTSUPP; in ptp_dp83640_enable()
494 index = rq->extts.index; in ptp_dp83640_enable()
496 return -EINVAL; in ptp_dp83640_enable()
500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, in ptp_dp83640_enable()
503 return -EINVAL; in ptp_dp83640_enable()
505 if (rq->extts.flags & PTP_FALLING_EDGE) in ptp_dp83640_enable()
510 mutex_lock(&clock->extreg_lock); in ptp_dp83640_enable()
512 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_enable()
517 if (rq->perout.flags) in ptp_dp83640_enable()
518 return -EOPNOTSUPP; in ptp_dp83640_enable()
519 if (rq->perout.index >= N_PER_OUT) in ptp_dp83640_enable()
520 return -EINVAL; in ptp_dp83640_enable()
521 return periodic_output(clock, rq, on, rq->perout.index); in ptp_dp83640_enable()
527 return -EOPNOTSUPP; in ptp_dp83640_enable()
536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && in ptp_dp83640_verify()
537 !list_empty(&clock->phylist)) in ptp_dp83640_verify()
551 struct dp83640_private *dp83640 = phydev->priv; in enable_status_frames()
552 struct dp83640_clock *clock = dp83640->clock; in enable_status_frames()
560 mutex_lock(&clock->extreg_lock); in enable_status_frames()
565 mutex_unlock(&clock->extreg_lock); in enable_status_frames()
567 if (!phydev->attached_dev) { in enable_status_frames()
569 "expected to find an attached netdevice\n"); in enable_status_frames()
574 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) in enable_status_frames()
577 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) in enable_status_frames()
587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) in is_status_frame()
595 return time_after(jiffies, rxts->tmo); in expired()
604 list_for_each_safe(this, next, &dp83640->rxts) { in prune_rx_ts()
607 list_del_init(&rxts->list); in prune_rx_ts()
608 list_add(&rxts->list, &dp83640->rxpool); in prune_rx_ts()
633 struct timespec64 ts; in recalibrate() local
635 struct phy_device *master = clock->chosen->phydev; in recalibrate()
639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); in recalibrate()
641 pr_err("PHY calibration pin not available - PHY is not calibrated."); in recalibrate()
645 mutex_lock(&clock->extreg_lock); in recalibrate()
650 list_for_each_entry(tmp, &clock->phylist, list) { in recalibrate()
651 enable_broadcast(tmp->phydev, clock->page, 1); in recalibrate()
652 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); in recalibrate()
653 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); in recalibrate()
654 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); in recalibrate()
656 enable_broadcast(master, clock->page, 1); in recalibrate()
668 list_for_each_entry(tmp, &clock->phylist, list) in recalibrate()
669 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); in recalibrate()
708 list_for_each_entry(tmp, &clock->phylist, list) { in recalibrate()
709 val = ext_read(tmp->phydev, PAGE4, PTP_STS); in recalibrate()
710 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); in recalibrate()
711 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); in recalibrate()
712 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); in recalibrate()
713 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
714 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
715 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
716 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
717 diff = now - (s64) phy2txts(&event_ts); in recalibrate()
718 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", in recalibrate()
721 ts = ns_to_timespec64(diff); in recalibrate()
722 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); in recalibrate()
728 list_for_each_entry(tmp, &clock->phylist, list) in recalibrate()
729 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); in recalibrate()
732 mutex_unlock(&clock->extreg_lock); in recalibrate()
770 dp83640->edata.sec_hi = phy_txts->sec_hi; in decode_evnt()
773 dp83640->edata.sec_lo = phy_txts->sec_lo; in decode_evnt()
776 dp83640->edata.ns_hi = phy_txts->ns_hi; in decode_evnt()
779 dp83640->edata.ns_lo = phy_txts->ns_lo; in decode_evnt()
783 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; in decode_evnt()
788 event.timestamp = phy2txts(&dp83640->edata); in decode_evnt()
791 event.timestamp -= 35; in decode_evnt()
796 ptp_clock_event(dp83640->clock->ptp_clock, &event); in decode_evnt()
812 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ in match()
820 if (rxts->msgtype != (msgtype & 0xf)) in match()
823 seqid = be16_to_cpu(hdr->sequence_id); in match()
824 if (rxts->seqid != seqid) in match()
828 (unsigned char *)&hdr->source_port_identity) >> 20; in match()
829 if (rxts->hash != hash) in match()
844 overflow = (phy_rxts->ns_hi >> 14) & 0x3; in decode_rxts()
848 spin_lock_irqsave(&dp83640->rx_lock, flags); in decode_rxts()
852 if (list_empty(&dp83640->rxpool)) { in decode_rxts()
856 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); in decode_rxts()
857 list_del_init(&rxts->list); in decode_rxts()
860 spin_lock(&dp83640->rx_queue.lock); in decode_rxts()
861 skb_queue_walk(&dp83640->rx_queue, skb) { in decode_rxts()
864 skb_info = (struct dp83640_skb_info *)skb->cb; in decode_rxts()
865 if (match(skb, skb_info->ptp_type, rxts)) { in decode_rxts()
866 __skb_unlink(skb, &dp83640->rx_queue); in decode_rxts()
869 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); in decode_rxts()
870 list_add(&rxts->list, &dp83640->rxpool); in decode_rxts()
874 spin_unlock(&dp83640->rx_queue.lock); in decode_rxts()
877 list_add_tail(&rxts->list, &dp83640->rxts); in decode_rxts()
879 spin_unlock_irqrestore(&dp83640->rx_lock, flags); in decode_rxts()
896 skb = skb_dequeue(&dp83640->tx_queue); in decode_txts()
902 overflow = (phy_txts->ns_hi >> 14) & 0x3; in decode_txts()
907 skb = skb_dequeue(&dp83640->tx_queue); in decode_txts()
911 skb_info = (struct dp83640_skb_info *)skb->cb; in decode_txts()
912 if (time_after(jiffies, skb_info->tmo)) { in decode_txts()
932 ptr = skb->data + 2; in decode_status_frame()
934 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { in decode_status_frame()
939 len -= sizeof(type); in decode_status_frame()
975 if (!list_empty(&clock->phylist)) { in dp83640_free_clocks()
976 pr_warn("phy list non-empty while unloading\n"); in dp83640_free_clocks()
979 list_del(&clock->list); in dp83640_free_clocks()
980 mutex_destroy(&clock->extreg_lock); in dp83640_free_clocks()
981 mutex_destroy(&clock->clock_lock); in dp83640_free_clocks()
982 put_device(&clock->bus->dev); in dp83640_free_clocks()
983 kfree(clock->caps.pin_config); in dp83640_free_clocks()
992 INIT_LIST_HEAD(&clock->list); in dp83640_clock_init()
993 clock->bus = bus; in dp83640_clock_init()
994 mutex_init(&clock->extreg_lock); in dp83640_clock_init()
995 mutex_init(&clock->clock_lock); in dp83640_clock_init()
996 INIT_LIST_HEAD(&clock->phylist); in dp83640_clock_init()
997 clock->caps.owner = THIS_MODULE; in dp83640_clock_init()
998 sprintf(clock->caps.name, "dp83640 timer"); in dp83640_clock_init()
999 clock->caps.max_adj = 1953124; in dp83640_clock_init()
1000 clock->caps.n_alarm = 0; in dp83640_clock_init()
1001 clock->caps.n_ext_ts = N_EXT_TS; in dp83640_clock_init()
1002 clock->caps.n_per_out = N_PER_OUT; in dp83640_clock_init()
1003 clock->caps.n_pins = DP83640_N_PINS; in dp83640_clock_init()
1004 clock->caps.pps = 0; in dp83640_clock_init()
1005 clock->caps.adjfine = ptp_dp83640_adjfine; in dp83640_clock_init()
1006 clock->caps.adjtime = ptp_dp83640_adjtime; in dp83640_clock_init()
1007 clock->caps.gettime64 = ptp_dp83640_gettime; in dp83640_clock_init()
1008 clock->caps.settime64 = ptp_dp83640_settime; in dp83640_clock_init()
1009 clock->caps.enable = ptp_dp83640_enable; in dp83640_clock_init()
1010 clock->caps.verify = ptp_dp83640_verify; in dp83640_clock_init()
1014 dp83640_gpio_defaults(clock->caps.pin_config); in dp83640_clock_init()
1018 get_device(&bus->dev); in dp83640_clock_init()
1024 if (chosen_phy == -1 && !clock->chosen) in choose_this_phy()
1027 if (chosen_phy == phydev->mdio.addr) in choose_this_phy()
1036 mutex_lock(&clock->clock_lock); in dp83640_clock_get()
1053 if (tmp->bus == bus) { in dp83640_clock_get_bus()
1065 clock->caps.pin_config = kcalloc(DP83640_N_PINS, in dp83640_clock_get_bus()
1068 if (!clock->caps.pin_config) { in dp83640_clock_get_bus()
1074 list_add_tail(&clock->list, &phyter_clocks); in dp83640_clock_get_bus()
1083 mutex_unlock(&clock->clock_lock); in dp83640_clock_put()
1105 struct dp83640_private *dp83640 = phydev->priv; in dp83640_config_init()
1106 struct dp83640_clock *clock = dp83640->clock; in dp83640_config_init()
1108 if (clock->chosen && !list_empty(&clock->phylist)) in dp83640_config_init()
1111 mutex_lock(&clock->extreg_lock); in dp83640_config_init()
1112 enable_broadcast(phydev, clock->page, 1); in dp83640_config_init()
1113 mutex_unlock(&clock->extreg_lock); in dp83640_config_init()
1118 mutex_lock(&clock->extreg_lock); in dp83640_config_init()
1120 mutex_unlock(&clock->extreg_lock); in dp83640_config_init()
1141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83640_config_intr()
1218 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ONESTEP_SYNC) in dp83640_hwtstamp()
1219 return -ERANGE; in dp83640_hwtstamp()
1221 dp83640->hwts_tx_en = cfg->tx_type; in dp83640_hwtstamp()
1223 switch (cfg->rx_filter) { in dp83640_hwtstamp()
1225 dp83640->hwts_rx_en = 0; in dp83640_hwtstamp()
1226 dp83640->layer = 0; in dp83640_hwtstamp()
1227 dp83640->version = 0; in dp83640_hwtstamp()
1232 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1233 dp83640->layer = PTP_CLASS_L4; in dp83640_hwtstamp()
1234 dp83640->version = PTP_CLASS_V1; in dp83640_hwtstamp()
1235 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in dp83640_hwtstamp()
1240 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1241 dp83640->layer = PTP_CLASS_L4; in dp83640_hwtstamp()
1242 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1243 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in dp83640_hwtstamp()
1248 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1249 dp83640->layer = PTP_CLASS_L2; in dp83640_hwtstamp()
1250 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1251 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in dp83640_hwtstamp()
1256 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1257 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; in dp83640_hwtstamp()
1258 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1259 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in dp83640_hwtstamp()
1262 return -ERANGE; in dp83640_hwtstamp()
1265 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; in dp83640_hwtstamp()
1266 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; in dp83640_hwtstamp()
1268 if (dp83640->layer & PTP_CLASS_L2) { in dp83640_hwtstamp()
1272 if (dp83640->layer & PTP_CLASS_L4) { in dp83640_hwtstamp()
1277 if (dp83640->hwts_tx_en) in dp83640_hwtstamp()
1280 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) in dp83640_hwtstamp()
1283 if (dp83640->hwts_rx_en) in dp83640_hwtstamp()
1286 mutex_lock(&dp83640->clock->extreg_lock); in dp83640_hwtstamp()
1288 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); in dp83640_hwtstamp()
1289 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); in dp83640_hwtstamp()
1291 mutex_unlock(&dp83640->clock->extreg_lock); in dp83640_hwtstamp()
1303 while ((skb = skb_dequeue(&dp83640->rx_queue))) { in rx_timestamp_work()
1306 skb_info = (struct dp83640_skb_info *)skb->cb; in rx_timestamp_work()
1307 if (!time_after(jiffies, skb_info->tmo)) { in rx_timestamp_work()
1308 skb_queue_head(&dp83640->rx_queue, skb); in rx_timestamp_work()
1315 if (!skb_queue_empty(&dp83640->rx_queue)) in rx_timestamp_work()
1316 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); in rx_timestamp_work()
1324 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; in dp83640_rxtstamp()
1336 if (!dp83640->hwts_rx_en) in dp83640_rxtstamp()
1339 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) in dp83640_rxtstamp()
1342 spin_lock_irqsave(&dp83640->rx_lock, flags); in dp83640_rxtstamp()
1344 list_for_each_safe(this, next, &dp83640->rxts) { in dp83640_rxtstamp()
1349 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); in dp83640_rxtstamp()
1350 list_del_init(&rxts->list); in dp83640_rxtstamp()
1351 list_add(&rxts->list, &dp83640->rxpool); in dp83640_rxtstamp()
1355 spin_unlock_irqrestore(&dp83640->rx_lock, flags); in dp83640_rxtstamp()
1358 skb_info->ptp_type = type; in dp83640_rxtstamp()
1359 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in dp83640_rxtstamp()
1360 skb_queue_tail(&dp83640->rx_queue, skb); in dp83640_rxtstamp()
1361 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); in dp83640_rxtstamp()
1372 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; in dp83640_txtstamp()
1376 switch (dp83640->hwts_tx_en) { in dp83640_txtstamp()
1385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in dp83640_txtstamp()
1386 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in dp83640_txtstamp()
1387 skb_queue_tail(&dp83640->tx_queue, skb); in dp83640_txtstamp()
1403 info->so_timestamping = in dp83640_ts_info()
1407 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); in dp83640_ts_info()
1408 info->tx_types = in dp83640_ts_info()
1412 info->rx_filters = in dp83640_ts_info()
1425 int err = -ENOMEM, i; in dp83640_probe()
1427 if (phydev->mdio.addr == BROADCAST_ADDR) in dp83640_probe()
1430 clock = dp83640_clock_get_bus(phydev->mdio.bus); in dp83640_probe()
1438 dp83640->phydev = phydev; in dp83640_probe()
1439 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; in dp83640_probe()
1440 dp83640->mii_ts.txtstamp = dp83640_txtstamp; in dp83640_probe()
1441 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; in dp83640_probe()
1442 dp83640->mii_ts.ts_info = dp83640_ts_info; in dp83640_probe()
1444 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); in dp83640_probe()
1445 INIT_LIST_HEAD(&dp83640->rxts); in dp83640_probe()
1446 INIT_LIST_HEAD(&dp83640->rxpool); in dp83640_probe()
1448 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); in dp83640_probe()
1451 phydev->default_timestamp = true; in dp83640_probe()
1452 phydev->mii_ts = &dp83640->mii_ts; in dp83640_probe()
1453 phydev->priv = dp83640; in dp83640_probe()
1455 spin_lock_init(&dp83640->rx_lock); in dp83640_probe()
1456 skb_queue_head_init(&dp83640->rx_queue); in dp83640_probe()
1457 skb_queue_head_init(&dp83640->tx_queue); in dp83640_probe()
1459 dp83640->clock = clock; in dp83640_probe()
1462 clock->chosen = dp83640; in dp83640_probe()
1463 clock->ptp_clock = ptp_clock_register(&clock->caps, in dp83640_probe()
1464 &phydev->mdio.dev); in dp83640_probe()
1465 if (IS_ERR(clock->ptp_clock)) { in dp83640_probe()
1466 err = PTR_ERR(clock->ptp_clock); in dp83640_probe()
1470 list_add_tail(&dp83640->list, &clock->phylist); in dp83640_probe()
1476 clock->chosen = NULL; in dp83640_probe()
1488 struct dp83640_private *tmp, *dp83640 = phydev->priv; in dp83640_remove()
1490 if (phydev->mdio.addr == BROADCAST_ADDR) in dp83640_remove()
1493 phydev->mii_ts = NULL; in dp83640_remove()
1496 cancel_delayed_work_sync(&dp83640->ts_work); in dp83640_remove()
1498 skb_queue_purge(&dp83640->rx_queue); in dp83640_remove()
1499 skb_queue_purge(&dp83640->tx_queue); in dp83640_remove()
1501 clock = dp83640_clock_get(dp83640->clock); in dp83640_remove()
1503 if (dp83640 == clock->chosen) { in dp83640_remove()
1504 ptp_clock_unregister(clock->ptp_clock); in dp83640_remove()
1505 clock->chosen = NULL; in dp83640_remove()
1507 list_for_each_safe(this, next, &clock->phylist) { in dp83640_remove()
1510 list_del_init(&tmp->list); in dp83640_remove()