Lines Matching full:phydev
50 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
53 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
56 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
59 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
62 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
65 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
68 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
71 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
76 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
82 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
85 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_d0_afe_config_init()
90 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_e0_plus_afe_config_init() argument
93 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
96 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
99 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
104 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
110 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
113 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_e0_plus_afe_config_init()
118 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_a0_patch_afe_config_init() argument
121 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
124 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
127 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
130 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
133 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
136 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
138 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_a0_patch_afe_config_init()
143 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) in bcm7xxx_28nm_config_init() argument
145 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); in bcm7xxx_28nm_config_init()
146 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); in bcm7xxx_28nm_config_init()
154 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_config_init()
157 phydev_name(phydev), phydev->drv->name, rev, patch); in bcm7xxx_28nm_config_init()
164 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_config_init()
169 ret = bcm_phy_28nm_a0b0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
172 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
178 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
181 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
190 ret = bcm_phy_enable_jumbo(phydev); in bcm7xxx_28nm_config_init()
194 ret = bcm_phy_downshift_get(phydev, &count); in bcm7xxx_28nm_config_init()
199 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_config_init()
203 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_28nm_config_init()
206 static int bcm7xxx_28nm_resume(struct phy_device *phydev) in bcm7xxx_28nm_resume() argument
211 ret = bcm7xxx_28nm_config_init(phydev); in bcm7xxx_28nm_resume()
220 return genphy_config_aneg(phydev); in bcm7xxx_28nm_resume()
254 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_01_afe_config_init() argument
259 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
274 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
284 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
291 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
300 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_apd_enable() argument
305 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, in bcm7xxx_28nm_ephy_apd_enable()
311 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in bcm7xxx_28nm_ephy_apd_enable()
317 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
325 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_eee_enable() argument
330 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
355 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
359 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
365 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
369 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
376 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
382 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
388 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_config_init() argument
390 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_ephy_config_init()
394 phydev_name(phydev), phydev->drv->name, rev); in bcm7xxx_28nm_ephy_config_init()
401 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_ephy_config_init()
405 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev); in bcm7xxx_28nm_ephy_config_init()
410 ret = bcm7xxx_28nm_ephy_eee_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
414 return bcm7xxx_28nm_ephy_apd_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
417 static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev) in bcm7xxx_16nm_ephy_afe_config() argument
422 tmp = genphy_soft_reset(phydev); in bcm7xxx_16nm_ephy_afe_config()
427 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006); in bcm7xxx_16nm_ephy_afe_config()
429 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
432 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
433 bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a); in bcm7xxx_16nm_ephy_afe_config()
436 bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1); in bcm7xxx_16nm_ephy_afe_config()
438 bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000); in bcm7xxx_16nm_ephy_afe_config()
441 bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68); in bcm7xxx_16nm_ephy_afe_config()
442 bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
447 bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036); in bcm7xxx_16nm_ephy_afe_config()
450 bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
452 bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002); in bcm7xxx_16nm_ephy_afe_config()
454 bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0); in bcm7xxx_16nm_ephy_afe_config()
456 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
459 bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010); in bcm7xxx_16nm_ephy_afe_config()
462 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038); in bcm7xxx_16nm_ephy_afe_config()
463 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b); in bcm7xxx_16nm_ephy_afe_config()
465 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f); in bcm7xxx_16nm_ephy_afe_config()
469 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82); in bcm7xxx_16nm_ephy_afe_config()
471 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82); in bcm7xxx_16nm_ephy_afe_config()
474 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82); in bcm7xxx_16nm_ephy_afe_config()
477 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86); in bcm7xxx_16nm_ephy_afe_config()
480 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86); in bcm7xxx_16nm_ephy_afe_config()
484 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea); in bcm7xxx_16nm_ephy_afe_config()
486 bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0); in bcm7xxx_16nm_ephy_afe_config()
489 tmp = bcm_phy_read_exp_sel(phydev, 0x00a9); in bcm7xxx_16nm_ephy_afe_config()
504 bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp); in bcm7xxx_16nm_ephy_afe_config()
506 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4); in bcm7xxx_16nm_ephy_afe_config()
510 bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002); in bcm7xxx_16nm_ephy_afe_config()
512 bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882); in bcm7xxx_16nm_ephy_afe_config()
516 bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201); in bcm7xxx_16nm_ephy_afe_config()
518 bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00); in bcm7xxx_16nm_ephy_afe_config()
523 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020); in bcm7xxx_16nm_ephy_afe_config()
526 bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
527 bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
530 bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800); in bcm7xxx_16nm_ephy_afe_config()
536 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
540 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
545 bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp); in bcm7xxx_16nm_ephy_afe_config()
546 bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp); in bcm7xxx_16nm_ephy_afe_config()
548 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
553 bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp); in bcm7xxx_16nm_ephy_afe_config()
558 static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_16nm_ephy_config_init() argument
562 ret = bcm7xxx_16nm_ephy_afe_config(phydev); in bcm7xxx_16nm_ephy_config_init()
566 ret = bcm_phy_set_eee(phydev, true); in bcm7xxx_16nm_ephy_config_init()
570 ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); in bcm7xxx_16nm_ephy_config_init()
582 ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); in bcm7xxx_16nm_ephy_config_init()
586 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_16nm_ephy_config_init()
589 static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_16nm_ephy_resume() argument
594 ret = bcm7xxx_16nm_ephy_config_init(phydev); in bcm7xxx_16nm_ephy_resume()
598 return genphy_config_aneg(phydev); in bcm7xxx_16nm_ephy_resume()
628 static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_read_mmd() argument
639 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_read_mmd()
645 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_read_mmd()
649 ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT); in bcm7xxx_28nm_ephy_read_mmd()
653 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
658 static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_write_mmd() argument
669 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_write_mmd()
675 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_write_mmd()
680 __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val); in bcm7xxx_28nm_ephy_write_mmd()
684 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
688 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_28nm_ephy_resume() argument
693 ret = bcm7xxx_28nm_ephy_config_init(phydev); in bcm7xxx_28nm_ephy_resume()
697 return genphy_config_aneg(phydev); in bcm7xxx_28nm_ephy_resume()
700 static int bcm7xxx_config_init(struct phy_device *phydev) in bcm7xxx_config_init() argument
705 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO); in bcm7xxx_config_init()
706 phy_read(phydev, MII_BCM7XXX_AUX_MODE); in bcm7xxx_config_init()
709 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
715 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
719 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
721 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
724 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
734 static int bcm7xxx_suspend(struct phy_device *phydev) in bcm7xxx_suspend() argument
751 ret = phy_write(phydev, in bcm7xxx_suspend()
761 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev, in bcm7xxx_28nm_get_tunable() argument
767 return bcm_phy_downshift_get(phydev, (u8 *)data); in bcm7xxx_28nm_get_tunable()
773 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev, in bcm7xxx_28nm_set_tunable() argument
782 ret = bcm_phy_downshift_set(phydev, count); in bcm7xxx_28nm_set_tunable()
795 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_set_tunable()
799 return genphy_restart_aneg(phydev); in bcm7xxx_28nm_set_tunable()
802 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev, in bcm7xxx_28nm_get_phy_stats() argument
805 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_get_phy_stats()
807 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm7xxx_28nm_get_phy_stats()
810 static int bcm7xxx_28nm_probe(struct phy_device *phydev) in bcm7xxx_28nm_probe() argument
816 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm7xxx_28nm_probe()
820 phydev->priv = priv; in bcm7xxx_28nm_probe()
822 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm7xxx_28nm_probe()
823 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm7xxx_28nm_probe()
828 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL); in bcm7xxx_28nm_probe()
838 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_probe()