18 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0  0x91E5 /* VDAL Control register */
25 	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);  in bcm_cygnus_afe_config()
26 	if (rc < 0)  in bcm_cygnus_afe_config()
30 	rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);  in bcm_cygnus_afe_config()
31 	if (rc < 0)  in bcm_cygnus_afe_config()
35 	rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);  in bcm_cygnus_afe_config()
36 	if (rc < 0)  in bcm_cygnus_afe_config()
40 	rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);  in bcm_cygnus_afe_config()
41 	if (rc < 0)  in bcm_cygnus_afe_config()
45 	rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);  in bcm_cygnus_afe_config()
46 	if (rc < 0)  in bcm_cygnus_afe_config()
49 	/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */  in bcm_cygnus_afe_config()
50 	rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);  in bcm_cygnus_afe_config()
51 	if (rc < 0)  in bcm_cygnus_afe_config()
55 	rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);  in bcm_cygnus_afe_config()
56 	if (rc < 0)  in bcm_cygnus_afe_config()
60 	rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB1, 0x10);  in bcm_cygnus_afe_config()
61 	if (rc < 0)  in bcm_cygnus_afe_config()
65 	rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x10);  in bcm_cygnus_afe_config()
66 	if (rc < 0)  in bcm_cygnus_afe_config()
70 	rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x00);  in bcm_cygnus_afe_config()
72 	return 0;  in bcm_cygnus_afe_config()
80 	if (reg < 0)  in bcm_cygnus_config_init()
131 	int ret = 0;  in bcm_omega_config_init()
135 	pr_info_once("%s: %s PHY revision: 0x%02x\n",  in bcm_omega_config_init()
140 	 * the MDIO management controller and make us return 0xffff for such  in bcm_omega_config_init()
146 	case 0x00:  in bcm_omega_config_init()
249 	return 0;  in bcm_omega_probe()
255 	.phy_id_mask   = 0xfffffff0,
265 	.phy_id_mask	= 0xfffffff0,
282 	{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
283 	{ PHY_ID_BCM_OMEGA, 0xfffffff0, },