net/pcs/pcs-xpcs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pcs/pcs-xpcs.h>
13 #define DW_VENDOR			BIT(15)
16 #define DW_USXGMII_RST			BIT(10)
17 #define DW_USXGMII_EN			BIT(9)
19 #define DW_VR_RST			BIT(15)
20 #define DW_EN_VSMMD1			BIT(13)
21 #define DW_CL37_BP			BIT(12)
28 #define DW_USXGMII_FULL			BIT(8)
29 #define DW_USXGMII_SS_MASK		(BIT(13) | BIT(6) | BIT(5))
30 #define DW_USXGMII_10000		(BIT(13) | BIT(6))
31 #define DW_USXGMII_5000			(BIT(13) | BIT(5))
32 #define DW_USXGMII_2500			(BIT(5))
33 #define DW_USXGMII_1000			(BIT(6))
34 #define DW_USXGMII_100			(BIT(13))
44 #define DW_C73_PAUSE			BIT(10)
45 #define DW_C73_ASYM_PAUSE		BIT(11)
48 #define DW_C73_1000KX			BIT(5)
49 #define DW_C73_10000KX4			BIT(6)
50 #define DW_C73_10000KR			BIT(7)
52 #define DW_C73_2500KX			BIT(0)
53 #define DW_C73_5000KR			BIT(1)
59 #define DW_VR_MII_MMD_STS_LINK_STS	BIT(2)
64 #define DW_VR_MII_DIG_CTRL1_2G5_EN	BIT(2)
71 #define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW		BIT(9)
72 #define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL	BIT(0)
75 #define DW_VR_MII_DIG_CTRL2_TX_POL_INV		BIT(4)
76 #define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)
79 #define DW_VR_MII_AN_CTRL_8BIT			BIT(8)
81 #define DW_VR_MII_TX_CONFIG_MASK		BIT(3)
88 #define DW_VR_MII_AN_INTR_EN			BIT(0)
91 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR	BIT(0)
92 #define DW_VR_MII_AN_STS_C37_ANSGM_FD		BIT(1)
98 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS		BIT(4)
101 #define AN_CL37_EN			BIT(12)	/* Enable Clause 37 auto-nego */
102 #define SGMII_SPEED_SS13		BIT(13)	/* SGMII speed along with SS6 */
103 #define SGMII_SPEED_SS6			BIT(6)	/* SGMII speed along with SS13 */
106 #define DW_HALF_DUPLEX			BIT(6)
107 #define DW_FULL_DUPLEX			BIT(5)
110 #define DW_VR_MII_EEE_LTX_EN			BIT(0)  /* LPI Tx Enable */
111 #define DW_VR_MII_EEE_LRX_EN			BIT(1)  /* LPI Rx Enable */
112 #define DW_VR_MII_EEE_TX_QUIET_EN		BIT(2)  /* Tx Quiet Enable */
113 #define DW_VR_MII_EEE_RX_QUIET_EN		BIT(3)  /* Rx Quiet Enable */
114 #define DW_VR_MII_EEE_TX_EN_CTRL		BIT(4)  /* Tx Control Enable */
115 #define DW_VR_MII_EEE_RX_EN_CTRL		BIT(7)  /* Rx Control Enable */
121 #define DW_VR_MII_EEE_TRN_LPI		BIT(0)	/* Transparent Mode Enable */