Lines Matching +full:0 +full:x8006

18 #define DW_VR_XS_PCS_DIG_CTRL1		0x0000
22 #define DW_VR_XS_PCS_DIG_STS		0x0010
25 #define DW_PSEQ_ST_GOOD			FIELD_PREP(GENMASK(4, 2), 0x4)
35 #define DW_USXGMII_10			(0)
38 #define DW_SR_AN_ADV1			0x10
39 #define DW_SR_AN_ADV2			0x11
40 #define DW_SR_AN_ADV3			0x12
46 #define DW_C73_AN_ADV_SF		0x1
52 #define DW_C73_2500KX			BIT(0)
57 #define DW_VR_MII_MMD_CTRL		0x0000
58 #define DW_VR_MII_MMD_STS		0x0001
60 #define DW_VR_MII_DIG_CTRL1		0x8000
61 #define DW_VR_MII_AN_CTRL		0x8001
62 #define DW_VR_MII_AN_INTR_STS		0x8002
66 #define DW_VR_MII_EEE_MCTRL0		0x8006
67 #define DW_VR_MII_EEE_MCTRL1		0x800b
68 #define DW_VR_MII_DIG_CTRL2		0x80e1
72 #define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL	BIT(0)
76 #define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)
82 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII	0x1
83 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII	0x0
86 #define DW_VR_MII_PCS_MODE_C37_1000BASEX	0x0
87 #define DW_VR_MII_PCS_MODE_C37_SGMII		0x2
88 #define DW_VR_MII_AN_INTR_EN			BIT(0)
91 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR	BIT(0)
95 #define DW_VR_MII_C37_ANSGM_SP_10		0x0
96 #define DW_VR_MII_C37_ANSGM_SP_100		0x1
97 #define DW_VR_MII_C37_ANSGM_SP_1000		0x2
109 /* VR MII EEE Control 0 defines */
110 #define DW_VR_MII_EEE_LTX_EN			BIT(0)  /* LPI Tx Enable */
121 #define DW_VR_MII_EEE_TRN_LPI		BIT(0)	/* Transparent Mode Enable */