Lines Matching +full:pll +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <linux/mdio-mux.h>
58 struct clk *pll; member
72 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); in g12a_ephy_pll_recalc_rate() local
75 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()
84 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); in g12a_ephy_pll_enable() local
85 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
87 /* Apply both enable an reset */ in g12a_ephy_pll_enable()
89 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
91 /* Clear the reset to let PLL lock */ in g12a_ephy_pll_enable()
93 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
97 * 31 may indicate that the PLL is not lock even though the clock in g12a_ephy_pll_enable()
100 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()
106 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); in g12a_ephy_pll_disable() local
109 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
112 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
117 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); in g12a_ephy_pll_is_enabled() local
120 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_is_enabled()
127 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); in g12a_ephy_pll_init() local
129 /* Apply PLL HW settings */ in g12a_ephy_pll_init()
130 writel(0x29c0040a, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_init()
131 writel(0x927e0000, pll->base + ETH_PLL_CTL1); in g12a_ephy_pll_init()
132 writel(0xac5f49e5, pll->base + ETH_PLL_CTL2); in g12a_ephy_pll_init()
133 writel(0x00000000, pll->base + ETH_PLL_CTL3); in g12a_ephy_pll_init()
134 writel(0x00000000, pll->base + ETH_PLL_CTL4); in g12a_ephy_pll_init()
135 writel(0x20200000, pll->base + ETH_PLL_CTL5); in g12a_ephy_pll_init()
136 writel(0x0000c002, pll->base + ETH_PLL_CTL6); in g12a_ephy_pll_init()
137 writel(0x00000023, pll->base + ETH_PLL_CTL7); in g12a_ephy_pll_init()
156 if (!__clk_is_enabled(priv->pll)) { in g12a_enable_internal_mdio()
157 ret = clk_prepare_enable(priv->pll); in g12a_enable_internal_mdio()
163 writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0); in g12a_enable_internal_mdio()
165 /* Make sure we get a 0 -> 1 transition on the enable bit */ in g12a_enable_internal_mdio()
171 writel(value, priv->regs + ETH_PHY_CNTL1); in g12a_enable_internal_mdio()
175 priv->regs + ETH_PHY_CNTL2); in g12a_enable_internal_mdio()
178 writel(value, priv->regs + ETH_PHY_CNTL1); in g12a_enable_internal_mdio()
188 /* Reset the mdio bus mux */ in g12a_enable_external_mdio()
189 writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2); in g12a_enable_external_mdio()
192 if (__clk_is_enabled(priv->pll)) in g12a_enable_external_mdio()
193 clk_disable_unprepare(priv->pll); in g12a_enable_external_mdio()
212 return -EINVAL; in g12a_mdio_switch_fn()
217 { .compatible = "amlogic,g12a-mdio-mux", },
227 struct g12a_ephy_pll *pll; in g12a_ephy_glue_clk_register() local
249 return -ENOMEM; in g12a_ephy_glue_clk_register()
253 return -ENOMEM; in g12a_ephy_glue_clk_register()
261 mux->reg = priv->regs + ETH_PLL_CTL0; in g12a_ephy_glue_clk_register()
262 mux->shift = __ffs(PLL_CTL0_SEL); in g12a_ephy_glue_clk_register()
263 mux->mask = PLL_CTL0_SEL >> mux->shift; in g12a_ephy_glue_clk_register()
264 mux->hw.init = &init; in g12a_ephy_glue_clk_register()
266 clk = devm_clk_register(dev, &mux->hw); in g12a_ephy_glue_clk_register()
273 /* create the pll */ in g12a_ephy_glue_clk_register()
274 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); in g12a_ephy_glue_clk_register()
275 if (!pll) in g12a_ephy_glue_clk_register()
276 return -ENOMEM; in g12a_ephy_glue_clk_register()
278 name = kasprintf(GFP_KERNEL, "%s#pll", dev_name(dev)); in g12a_ephy_glue_clk_register()
280 return -ENOMEM; in g12a_ephy_glue_clk_register()
289 pll->base = priv->regs; in g12a_ephy_glue_clk_register()
290 pll->hw.init = &init; in g12a_ephy_glue_clk_register()
292 clk = devm_clk_register(dev, &pll->hw); in g12a_ephy_glue_clk_register()
299 priv->pll = clk; in g12a_ephy_glue_clk_register()
306 struct device *dev = &pdev->dev; in g12a_mdio_mux_probe()
313 return -ENOMEM; in g12a_mdio_mux_probe()
317 priv->regs = devm_platform_ioremap_resource(pdev, 0); in g12a_mdio_mux_probe()
318 if (IS_ERR(priv->regs)) in g12a_mdio_mux_probe()
319 return PTR_ERR(priv->regs); in g12a_mdio_mux_probe()
326 /* Register PLL in CCF */ in g12a_mdio_mux_probe()
331 ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn, in g12a_mdio_mux_probe()
332 &priv->mux_handle, dev, NULL); in g12a_mdio_mux_probe()
343 mdio_mux_uninit(priv->mux_handle); in g12a_mdio_mux_remove()
345 if (__clk_is_enabled(priv->pll)) in g12a_mdio_mux_remove()
346 clk_disable_unprepare(priv->pll); in g12a_mdio_mux_remove()
353 .name = "g12a-mdio_mux",