Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
30 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
31 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
32 [GENQMB_AOOOWR] = BIT(20),
33 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
35 /* Bits 25-29 reserved */
36 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
37 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
43 [CLKON_RX] = BIT(0),
44 [CLKON_PROC] = BIT(1),
45 [TX_WRAPPER] = BIT(2),
46 [CLKON_MISC] = BIT(3),
47 [RAM_ARB] = BIT(4),
48 [FTCH_HPS] = BIT(5),
49 [FTCH_DPS] = BIT(6),
50 [CLKON_HPS] = BIT(7),
51 [CLKON_DPS] = BIT(8),
52 [RX_HPS_CMDQS] = BIT(9),
53 [HPS_DPS_CMDQS] = BIT(10),
54 [DPS_TX_CMDQS] = BIT(11),
55 [RSRC_MNGR] = BIT(12),
56 [CTX_HANDLER] = BIT(13),
57 [ACK_MNGR] = BIT(14),
58 [D_DCPH] = BIT(15),
59 [H_DCPH] = BIT(16),
60 [CLKON_DCMP] = BIT(17),
61 [NTF_TX_CMDQS] = BIT(18),
62 [CLKON_TX_0] = BIT(19),
63 [CLKON_TX_1] = BIT(20),
64 [CLKON_FNR] = BIT(21),
65 [QSB2AXI_CMDQ_L] = BIT(22),
66 [AGGR_WRAPPER] = BIT(23),
67 [RAM_SLAVEWAY] = BIT(24),
68 [CLKON_QMB] = BIT(25),
69 [WEIGHT_ARB] = BIT(26),
70 [GSI_IF] = BIT(27),
71 [CLKON_GLOBAL] = BIT(28),
72 [GLOBAL_2X_CLK] = BIT(29),
73 [DPL_FIFO] = BIT(30),
74 [DRBIP] = BIT(31),
80 [ROUTE_DIS] = BIT(0),
82 [ROUTE_DEF_HDR_TABLE] = BIT(6),
85 /* Bits 22-23 reserved */
86 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
87 /* Bits 25-31 reserved */
102 /* Bits 8-31 reserved */
110 /* Bits 8-15 reserved */
118 [IPV6_ROUTER_HASH] = BIT(0),
119 /* Bits 1-3 reserved */
120 [IPV6_FILTER_HASH] = BIT(4),
121 /* Bits 5-7 reserved */
122 [IPV4_ROUTER_HASH] = BIT(8),
123 /* Bits 9-11 reserved */
124 [IPV4_FILTER_HASH] = BIT(12),
125 /* Bits 13-31 reserved */
130 /* Valid bits defined by ipa->available */
135 /* Bits 18-31 reserved */
141 /* Valid bits defined by ipa->available */
145 /* Bits 0-1 reserved */
148 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
149 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
150 [PA_MASK_EN] = BIT(12),
151 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
152 [DUAL_TX_ENABLE] = BIT(17),
153 [SSPND_PA_NO_START_STATE] = BIT(18),
154 /* Bits 19-31 reserved */
161 /* Bits 4-7 reserved */
163 /* Bits 13-15 reserved */
165 /* Bits 21-23 reserved */
167 /* Bits 28-31 reserved */
174 [CONST_NON_IDLE_ENABLE] = BIT(16),
175 /* Bits 17-31 reserved */
182 /* Bits 5-6 reserved */
183 [DPL_TIMESTAMP_SEL] = BIT(7),
185 /* Bits 13-15 reserved */
187 /* Bits 21-31 reserved */
194 /* Bits 9-30 reserved */
195 [DIV_ENABLE] = BIT(31),
210 /* Bits 6-7 reserved */
211 [X_MAX_LIM] = GENMASK(13, 8),
212 /* Bits 14-15 reserved */
214 /* Bits 22-23 reserved */
216 /* Bits 30-31 reserved */
224 /* Bits 6-7 reserved */
225 [X_MAX_LIM] = GENMASK(13, 8),
226 /* Bits 14-15 reserved */
228 /* Bits 22-23 reserved */
230 /* Bits 30-31 reserved */
238 /* Bits 6-7 reserved */
239 [X_MAX_LIM] = GENMASK(13, 8),
240 /* Bits 14-15 reserved */
242 /* Bits 22-23 reserved */
244 /* Bits 30-31 reserved */
252 /* Bits 6-7 reserved */
253 [X_MAX_LIM] = GENMASK(13, 8),
254 /* Bits 14-15 reserved */
256 /* Bits 22-23 reserved */
258 /* Bits 30-31 reserved */
265 [FRAG_OFFLOAD_EN] = BIT(0),
268 /* Bit 7 reserved */
269 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
270 /* Bits 9-31 reserved */
277 /* Bits 2-31 reserved */
284 [HDR_OFST_METADATA_VALID] = BIT(6),
286 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
287 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
289 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
297 [HDR_ENDIANNESS] = BIT(0),
298 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
299 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
300 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
302 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
303 /* Bits 14-15 reserved */
307 /* Bits 22-31 reserved */
317 [DCPH_ENABLE] = BIT(3),
319 /* Bits 9-11 reserved */
321 [PIPE_REPLICATION_EN] = BIT(28),
322 [PAD_EN] = BIT(29),
323 [DRBIP_ACL_ENABLE] = BIT(30),
324 /* Bit 31 reserved */
333 /* Bit 11 reserved */
336 [SW_EOF_ACTIVE] = BIT(23),
337 [FORCE_CLOSE] = BIT(24),
338 /* Bit 25 reserved */
339 [HARD_BYTE_LIMIT_EN] = BIT(26),
340 [AGGR_GRAN_SEL] = BIT(27),
341 /* Bits 28-31 reserved */
347 [HOL_BLOCK_EN] = BIT(0),
348 /* Bits 1-31 reserved */
356 /* Bits 5-7 reserved */
357 [TIMER_GRAN_SEL] = BIT(8),
358 /* Bits 9-31 reserved */
366 [SYSPIPE_ERR_DETECTION] = BIT(6),
367 [PACKET_OFFSET_VALID] = BIT(7),
368 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
369 [IGNORE_MIN_PKT_ERR] = BIT(14),
370 /* Bit 15 reserved */
378 /* Bits 2-31 reserved */
385 /* Bits 8-31 reserved */
391 [STATUS_EN] = BIT(0),
393 /* Bits 6-8 reserved */
394 [STATUS_PKT_SUPPRESS] = BIT(9),
395 /* Bits 10-31 reserved */
401 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
402 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
403 [FILTER_HASH_MSK_DST_IP] = BIT(2),
404 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
405 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
406 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
407 [FILTER_HASH_MSK_METADATA] = BIT(6),
409 /* Bits 7-15 reserved */
410 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
411 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
412 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
413 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
414 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
415 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
416 [ROUTER_HASH_MSK_METADATA] = BIT(22),
418 /* Bits 23-31 reserved */
434 [UC_INTR] = BIT(0),
435 /* Bits 1-31 reserved */
440 /* Valid bits defined by ipa->available */
444 /* Valid bits defined by ipa->available */
448 /* Valid bits defined by ipa->available */