Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
31 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
32 /* Bits 22-31 reserved */
38 [CLKON_RX] = BIT(0),
39 [CLKON_PROC] = BIT(1),
40 [TX_WRAPPER] = BIT(2),
41 [CLKON_MISC] = BIT(3),
42 [RAM_ARB] = BIT(4),
43 [FTCH_HPS] = BIT(5),
44 [FTCH_DPS] = BIT(6),
45 [CLKON_HPS] = BIT(7),
46 [CLKON_DPS] = BIT(8),
47 [RX_HPS_CMDQS] = BIT(9),
48 [HPS_DPS_CMDQS] = BIT(10),
49 [DPS_TX_CMDQS] = BIT(11),
50 [RSRC_MNGR] = BIT(12),
51 [CTX_HANDLER] = BIT(13),
52 [ACK_MNGR] = BIT(14),
53 [D_DCPH] = BIT(15),
54 [H_DCPH] = BIT(16),
55 [CLKON_DCMP] = BIT(17),
56 [NTF_TX_CMDQS] = BIT(18),
57 [CLKON_TX_0] = BIT(19),
58 [CLKON_TX_1] = BIT(20),
59 [CLKON_FNR] = BIT(21),
60 [QSB2AXI_CMDQ_L] = BIT(22),
61 [AGGR_WRAPPER] = BIT(23),
62 [RAM_SLAVEWAY] = BIT(24),
63 [CLKON_QMB] = BIT(25),
64 [WEIGHT_ARB] = BIT(26),
65 [GSI_IF] = BIT(27),
66 [CLKON_GLOBAL] = BIT(28),
67 [GLOBAL_2X_CLK] = BIT(29),
68 [DPL_FIFO] = BIT(30),
69 [DRBIP] = BIT(31),
75 [ROUTE_DIS] = BIT(0),
77 [ROUTE_DEF_HDR_TABLE] = BIT(6),
80 /* Bits 22-23 reserved */
81 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
82 /* Bits 25-31 reserved */
97 /* Bits 8-31 reserved */
105 /* Bits 8-15 reserved */
113 [IPV6_ROUTER_HASH] = BIT(0),
114 /* Bits 1-3 reserved */
115 [IPV6_FILTER_HASH] = BIT(4),
116 /* Bits 5-7 reserved */
117 [IPV4_ROUTER_HASH] = BIT(8),
118 /* Bits 9-11 reserved */
119 [IPV4_FILTER_HASH] = BIT(12),
120 /* Bits 13-31 reserved */
125 /* Valid bits defined by ipa->available */
130 /* Bits 18-31 reserved */
136 /* Valid bits defined by ipa->available */
140 /* Bits 0-1 reserved */
143 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
144 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
145 [PA_MASK_EN] = BIT(12),
146 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
147 [DUAL_TX_ENABLE] = BIT(17),
148 [SSPND_PA_NO_START_STATE] = BIT(18),
149 /* Bits 19-31 reserved */
156 /* Bits 4-7 reserved */
158 /* Bits 13-15 reserved */
160 /* Bits 21-23 reserved */
162 /* Bits 28-31 reserved */
169 [CONST_NON_IDLE_ENABLE] = BIT(16),
170 /* Bits 17-31 reserved */
177 /* Bits 5-6 reserved */
178 [DPL_TIMESTAMP_SEL] = BIT(7),
180 /* Bits 13-15 reserved */
182 /* Bits 21-31 reserved */
189 /* Bits 9-30 reserved */
190 [DIV_ENABLE] = BIT(31),
205 /* Bits 6-7 reserved */
206 [X_MAX_LIM] = GENMASK(13, 8),
207 /* Bits 14-15 reserved */
209 /* Bits 22-23 reserved */
211 /* Bits 30-31 reserved */
219 /* Bits 6-7 reserved */
220 [X_MAX_LIM] = GENMASK(13, 8),
221 /* Bits 14-15 reserved */
223 /* Bits 22-23 reserved */
225 /* Bits 30-31 reserved */
233 /* Bits 6-7 reserved */
234 [X_MAX_LIM] = GENMASK(13, 8),
235 /* Bits 14-15 reserved */
237 /* Bits 22-23 reserved */
239 /* Bits 30-31 reserved */
247 /* Bits 6-7 reserved */
248 [X_MAX_LIM] = GENMASK(13, 8),
249 /* Bits 14-15 reserved */
251 /* Bits 22-23 reserved */
253 /* Bits 30-31 reserved */
260 [FRAG_OFFLOAD_EN] = BIT(0),
263 /* Bit 7 reserved */
264 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
265 /* Bits 9-31 reserved */
272 /* Bits 2-31 reserved */
279 [HDR_OFST_METADATA_VALID] = BIT(6),
281 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
282 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
284 [HDR_A5_MUX] = BIT(26),
285 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
293 [HDR_ENDIANNESS] = BIT(0),
294 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
295 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
296 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
298 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
299 /* Bits 14-15 reserved */
303 /* Bits 22-31 reserved */
313 [DCPH_ENABLE] = BIT(3),
315 /* Bits 9-11 reserved */
317 [PIPE_REPLICATION_EN] = BIT(28),
318 [PAD_EN] = BIT(29),
319 /* Bits 30-31 reserved */
328 /* Bit 11 reserved */
331 [SW_EOF_ACTIVE] = BIT(23),
332 [FORCE_CLOSE] = BIT(24),
333 /* Bit 25 reserved */
334 [HARD_BYTE_LIMIT_EN] = BIT(26),
335 [AGGR_GRAN_SEL] = BIT(27),
336 /* Bits 28-31 reserved */
342 [HOL_BLOCK_EN] = BIT(0),
343 /* Bits 1-31 reserved */
351 /* Bits 5-7 reserved */
352 [TIMER_GRAN_SEL] = BIT(8),
353 /* Bits 9-31 reserved */
361 [SYSPIPE_ERR_DETECTION] = BIT(6),
362 [PACKET_OFFSET_VALID] = BIT(7),
363 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
364 [IGNORE_MIN_PKT_ERR] = BIT(14),
365 /* Bit 15 reserved */
372 [ENDP_RSRC_GRP] = BIT(0),
373 /* Bits 1-31 reserved */
380 /* Bits 8-31 reserved */
386 [STATUS_EN] = BIT(0),
388 /* Bits 6-8 reserved */
389 [STATUS_PKT_SUPPRESS] = BIT(9),
390 /* Bits 10-31 reserved */
396 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
397 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
398 [FILTER_HASH_MSK_DST_IP] = BIT(2),
399 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
400 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
401 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
402 [FILTER_HASH_MSK_METADATA] = BIT(6),
404 /* Bits 7-15 reserved */
405 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
406 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
407 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
408 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
409 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
410 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
411 [ROUTER_HASH_MSK_METADATA] = BIT(22),
413 /* Bits 23-31 reserved */
429 [UC_INTR] = BIT(0),
430 /* Bits 1-31 reserved */
435 /* Valid bits defined by ipa->available */
439 /* Valid bits defined by ipa->available */
443 /* Valid bits defined by ipa->available */