200 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_type_update()
228 	iowrite32(~0, gsi->virt + reg_offset(reg));  in gsi_irq_ev_ctrl_enable()
231 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_ev_ctrl_enable()
243 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_ev_ctrl_disable()
261 	iowrite32(~0, gsi->virt + reg_offset(reg));  in gsi_irq_ch_ctrl_enable()
264 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_ch_ctrl_enable()
277 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_ch_ctrl_disable()
290 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_ieob_enable_one()
310 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_ieob_disable()
328 	iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));  in gsi_irq_enable()
341 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_irq_enable()
355 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_disable()
358 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_disable()
365 	return ring->virt + (index % ring->count) * GSI_RING_ELEMENT_SIZE;  in gsi_ring_virt()
391 	iowrite32(val, gsi->virt + reg);  in gsi_command()
403 	val = ioread32(gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_state()
514 	void __iomem *virt = gsi->virt;  in gsi_channel_state()  local
518 	val = ioread32(virt + reg_n_offset(reg, channel_id));  in gsi_channel_state()
712 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_doorbell()
729 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
733 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
741 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
745 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
752 	iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
756 	iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
759 	iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
762 	iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
766 	iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
769 	iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));  in gsi_evt_ring_program()
844 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
850 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
858 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
862 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
891 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
901 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
905 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
909 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_program()
917 	val = ioread32(gsi->virt + offset);  in gsi_channel_program()
919 	iowrite32(val, gsi->virt + offset);  in gsi_channel_program()
1139 	channel_mask = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_chan_ctrl()
1142 	iowrite32(channel_mask, gsi->virt + reg_offset(reg));  in gsi_isr_chan_ctrl()
1160 	event_mask = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_evt_ctrl()
1163 	iowrite32(event_mask, gsi->virt + reg_offset(reg));  in gsi_isr_evt_ctrl()
1223 	val = ioread32(gsi->virt + offset);  in gsi_isr_glob_err()
1224 	iowrite32(0, gsi->virt + offset);  in gsi_isr_glob_err()
1227 	iowrite32(~0, gsi->virt + reg_offset(clr_reg));  in gsi_isr_glob_err()
1270 	val = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_gp_int1()
1299 	val = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_glob_ee()
1305 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_isr_glob_ee()
1325 	event_mask = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_ieob()
1330 	iowrite32(event_mask, gsi->virt + reg_offset(reg));  in gsi_isr_ieob()
1349 	val = ioread32(gsi->virt + reg_offset(reg));  in gsi_isr_general()
1352 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_isr_general()
1377 	while ((intr_mask = ioread32(gsi->virt + offset))) {  in gsi_isr()
1544 	ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL);  in gsi_ring_alloc()
1545 	if (!ring->virt)  in gsi_ring_alloc()
1560 	dma_free_coherent(gsi->dev, size, ring->virt, ring->addr);  in gsi_ring_free()
1597 	iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));  in gsi_channel_doorbell()
1620 	index = gsi_ring_index(ring, ioread32(gsi->virt + offset));  in gsi_channel_update()
1786 	iowrite32(val, gsi->virt + reg_offset(reg));  in gsi_generic_command()
1791 	val = ioread32(gsi->virt + offset);  in gsi_generic_command()
1794 	iowrite32(val, gsi->virt + offset);  in gsi_generic_command()
1808 	iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));  in gsi_generic_command()
1970 	iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1977 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1980 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1983 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1986 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1991 		iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1994 		iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
1998 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_irq_setup()
2029 	val = ioread32(gsi->virt + reg_offset(reg));  in gsi_ring_setup()
2073 	val = ioread32(gsi->virt + reg_offset(reg));  in gsi_setup()
2089 	iowrite32(0, gsi->virt + reg_offset(reg));  in gsi_setup()