Lines Matching +full:4 +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
169 /*------------------- 0x5C */
170 /*------------------- 0x5D */
185 /*------------------- 0x6C */
186 /*------------------- 0x6D */
191 /*------------------- 0x72 */
192 /*------------------- 0x73 */
195 /*------------------- 0x76 */
196 /*------------------- 0x77 */
209 /*------------------- 0x84 */
210 /*------------------- 0x85 */
212 /*------------------- 0x87 */
213 /*------------------- 0x88 */
216 /*------------------- 0x8B */
217 /*------------------- 0x8C */
220 /*------------------- 0x8F */
221 /*------------------- 0x90 */
224 /*------------------- 0x93 */
225 /*------------------- 0x94 */
230 /*------------------- 0x99 */
239 /*------------------- 0xA2 */
246 /*------------------- 0xA9 */
256 /* IRQSTS1 bits */
260 #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4)
266 /* IRQSTS2 bits */
270 #define DAR_IRQSTS2_PI BIT(4)
276 /* IRQSTS3 bits */
280 #define DAR_IRQSTS3_TMR1MSK BIT(4)
286 /* PHY_CTRL1 bits */
291 #define DAR_PHY_CTRL1_RXACKRQD BIT(4)
295 /* PHY_CTRL2 bits */
299 #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4)
305 /* PHY_CTRL3 bits */
309 #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4)
314 /* RX_FRM_LEN bits */
317 /* PHY_CTRL4 bits */
328 /* SRC_CTRL bits */
330 #define DAR_SRC_CTRL_INDEX_SHIFT (4)
336 /* DAR_ASM_CTRL1 bits */
340 #define DAR_ASM_CTRL1_CTR BIT(4)
345 /* DAR_ASM_CTRL2 bits */
350 /* DAR_CLK_OUT_CTRL bits */
354 #define DAR_CLK_OUT_CTRL_DS BIT(4)
358 /* DAR_PWR_MODES bits */
360 #define DAR_PWR_MODES_XTALEN BIT(4)
365 /* RX_FRAME_FILTER bits */
369 #define IAR_RX_FRAME_FLT_NS_FT BIT(4)
375 /* DUAL_PAN_CTRL bits */
377 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4)
383 /* DUAL_PAN_STS bits */
388 /* CCA_CTRL bits */
391 #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4)
397 /* ANT_PAD_CTRL bits */
399 #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4)
404 /* MISC_PAD_CTRL bits */
410 /* ANT_AGC_CTRL bits */
416 /* BSM_CTRL bits */
419 /* SOFT_RESET bits */
421 #define IAR_SOFT_RESET_REGS_RST BIT(4)
427 /* SEQ_MGR_CTRL bits */
431 #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
437 /* SEQ_MGR_STS bits */
441 #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
445 /* ABORT_STS bits */
450 /* IAR_FILTERFAIL_CODE2 bits */
454 /* PHY_STS bits */
463 /* TESTMODE_CTRL bits */
464 #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4)
470 /* DTM_CTRL1 bits */
474 #define IAR_DTM_CTRL1_PAGE4 BIT(4)
481 #define IAR_TX_MODE_CTRL_TX_INV BIT(4)