Lines Matching +full:filt +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
49 MCR20A_CCA_ED, // energy detect - CCA bit not active,
51 MCR20A_CCA_MODE1, // energy detect - CCA bit ACTIVE
52 MCR20A_CCA_MODE2, // 802.15.4 compliant signal detect - CCA bit ACTIVE
65 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
127 #define printdev(X) (&X->spi->dev)
451 lp->reg_msg.complete = NULL; in mcr20a_write_tx_buf_complete()
452 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1); in mcr20a_write_tx_buf_complete()
453 lp->reg_data[0] = MCR20A_XCVSEQ_TX; in mcr20a_write_tx_buf_complete()
454 lp->reg_xfer_data.len = 1; in mcr20a_write_tx_buf_complete()
456 ret = spi_async(lp->spi, &lp->reg_msg); in mcr20a_write_tx_buf_complete()
464 struct mcr20a_local *lp = hw->priv; in mcr20a_xmit()
468 lp->tx_skb = skb; in mcr20a_xmit()
471 skb->data, skb->len, 0); in mcr20a_xmit()
473 lp->is_tx = 1; in mcr20a_xmit()
475 lp->reg_msg.complete = NULL; in mcr20a_xmit()
476 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1); in mcr20a_xmit()
477 lp->reg_data[0] = MCR20A_XCVSEQ_IDLE; in mcr20a_xmit()
478 lp->reg_xfer_data.len = 1; in mcr20a_xmit()
480 return spi_async(lp->spi, &lp->reg_msg); in mcr20a_xmit()
494 struct mcr20a_local *lp = hw->priv; in mcr20a_set_channel()
500 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]); in mcr20a_set_channel()
503 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00); in mcr20a_set_channel()
506 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB, in mcr20a_set_channel()
507 PLL_FRAC[channel - 11]); in mcr20a_set_channel()
517 struct mcr20a_local *lp = hw->priv; in mcr20a_start()
524 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_start()
530 enable_irq(lp->spi->irq); in mcr20a_start()
533 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2, in mcr20a_start()
540 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_start()
551 struct mcr20a_local *lp = hw->priv; in mcr20a_stop()
556 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_stop()
559 /* disable irq */ in mcr20a_stop()
560 disable_irq(lp->spi->irq); in mcr20a_stop()
565 struct ieee802154_hw_addr_filt *filt, in mcr20a_set_hw_addr_filt() argument
568 struct mcr20a_local *lp = hw->priv; in mcr20a_set_hw_addr_filt()
573 u16 addr = le16_to_cpu(filt->short_addr); in mcr20a_set_hw_addr_filt()
575 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr); in mcr20a_set_hw_addr_filt()
576 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8); in mcr20a_set_hw_addr_filt()
580 u16 pan = le16_to_cpu(filt->pan_id); in mcr20a_set_hw_addr_filt()
582 regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan); in mcr20a_set_hw_addr_filt()
583 regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8); in mcr20a_set_hw_addr_filt()
589 memcpy(addr, &filt->ieee_addr, 8); in mcr20a_set_hw_addr_filt()
591 regmap_write(lp->regmap_iar, in mcr20a_set_hw_addr_filt()
596 if (filt->pan_coord) { in mcr20a_set_hw_addr_filt()
597 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_hw_addr_filt()
600 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_hw_addr_filt()
608 /* -30 dBm to 10 dBm */
611 -3000, -2800, -2600, -2400, -2200, -2000, -1800, -1600, -1400,
612 -1200, -1000, -800, -600, -400, -200, 0, 200, 400, 600, 800, 1000
618 struct mcr20a_local *lp = hw->priv; in mcr20a_set_txpower()
623 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) { in mcr20a_set_txpower()
624 if (lp->hw->phy->supported.tx_powers[i] == mbm) in mcr20a_set_txpower()
625 return regmap_write(lp->regmap_dar, DAR_PA_PWR, in mcr20a_set_txpower()
629 return -EINVAL; in mcr20a_set_txpower()
639 struct mcr20a_local *lp = hw->priv; in mcr20a_set_cca_mode()
647 switch (cca->mode) { in mcr20a_set_cca_mode()
655 switch (cca->opt) { in mcr20a_set_cca_mode()
665 return -EINVAL; in mcr20a_set_cca_mode()
669 return -EINVAL; in mcr20a_set_cca_mode()
671 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_cca_mode()
679 ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL, in mcr20a_set_cca_mode()
683 ret = regmap_update_bits(lp->regmap_iar, in mcr20a_set_cca_mode()
698 struct mcr20a_local *lp = hw->priv; in mcr20a_set_cca_ed_level()
703 for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) { in mcr20a_set_cca_ed_level()
704 if (hw->phy->supported.cca_ed_levels[i] == mbm) in mcr20a_set_cca_ed_level()
705 return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i); in mcr20a_set_cca_ed_level()
714 struct mcr20a_local *lp = hw->priv; in mcr20a_set_promiscuous_mode()
726 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_promiscuous_mode()
732 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_set_promiscuous_mode()
737 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_promiscuous_mode()
742 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_set_promiscuous_mode()
774 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_request_rx()
784 u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK; in mcr20a_handle_rx_read_buf_complete()
792 dev_vdbg(&lp->spi->dev, "corrupted frame received\n"); in mcr20a_handle_rx_read_buf_complete()
796 len = len - 2; /* get rid of frame check field */ in mcr20a_handle_rx_read_buf_complete()
802 __skb_put_data(skb, lp->rx_buf, len); in mcr20a_handle_rx_read_buf_complete()
803 ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]); in mcr20a_handle_rx_read_buf_complete()
806 lp->rx_buf, len, 0); in mcr20a_handle_rx_read_buf_complete()
807 pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]); in mcr20a_handle_rx_read_buf_complete()
823 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK; in mcr20a_handle_rx_read_len_complete()
827 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete; in mcr20a_handle_rx_read_len_complete()
828 lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF; in mcr20a_handle_rx_read_len_complete()
829 lp->rx_xfer_buf.len = len; in mcr20a_handle_rx_read_len_complete()
831 ret = spi_async(lp->spi, &lp->rx_buf_msg); in mcr20a_handle_rx_read_len_complete()
840 lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete; in mcr20a_handle_rx()
841 lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN); in mcr20a_handle_rx()
842 lp->reg_xfer_data.len = 1; in mcr20a_handle_rx()
844 return spi_async(lp->spi, &lp->reg_msg); in mcr20a_handle_rx()
852 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false); in mcr20a_handle_tx_complete()
865 lp->tx_header[0] = MCR20A_BURST_WRITE_PACKET_BUF; in mcr20a_handle_tx()
867 lp->tx_len[0] = lp->tx_skb->len + 2; in mcr20a_handle_tx()
868 lp->tx_xfer_buf.tx_buf = lp->tx_skb->data; in mcr20a_handle_tx()
870 lp->tx_xfer_buf.len = lp->tx_skb->len + 1; in mcr20a_handle_tx()
872 ret = spi_async(lp->spi, &lp->tx_buf_msg); in mcr20a_handle_tx()
885 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete()
889 enable_irq(lp->spi->irq); in mcr20a_irq_clean_complete()
892 lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]); in mcr20a_irq_clean_complete()
897 if (lp->is_tx) { in mcr20a_irq_clean_complete()
898 lp->is_tx = 0; in mcr20a_irq_clean_complete()
909 if (lp->is_tx) { in mcr20a_irq_clean_complete()
911 lp->is_tx = 0; in mcr20a_irq_clean_complete()
921 if (lp->is_tx) { in mcr20a_irq_clean_complete()
937 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_irq_status_complete()
940 lp->reg_msg.complete = mcr20a_irq_clean_complete; in mcr20a_irq_status_complete()
941 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1); in mcr20a_irq_status_complete()
942 memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM); in mcr20a_irq_status_complete()
943 lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM; in mcr20a_irq_status_complete()
945 ret = spi_async(lp->spi, &lp->reg_msg); in mcr20a_irq_status_complete()
958 lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1); in mcr20a_irq_isr()
960 ret = spi_async(lp->spi, &lp->irq_msg); in mcr20a_irq_isr()
972 struct ieee802154_hw *hw = lp->hw; in mcr20a_hw_setup()
973 struct wpan_phy *phy = lp->hw->phy; in mcr20a_hw_setup()
977 hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | in mcr20a_hw_setup()
981 phy->flags = WPAN_PHY_FLAG_TXPOWER | WPAN_PHY_FLAG_CCA_ED_LEVEL | in mcr20a_hw_setup()
984 phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | in mcr20a_hw_setup()
986 phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) | in mcr20a_hw_setup()
992 mcr20a_ed_levels[i] = -i * 100; in mcr20a_hw_setup()
995 phy->supported.cca_ed_levels = mcr20a_ed_levels; in mcr20a_hw_setup()
996 phy->supported.cca_ed_levels_size = ARRAY_SIZE(mcr20a_ed_levels); in mcr20a_hw_setup()
998 phy->cca.mode = NL802154_CCA_ENERGY; in mcr20a_hw_setup()
1000 phy->supported.channels[0] = MCR20A_VALID_CHANNELS; in mcr20a_hw_setup()
1001 phy->current_page = 0; in mcr20a_hw_setup()
1003 phy->current_channel = 20; in mcr20a_hw_setup()
1004 phy->supported.tx_powers = mcr20a_powers; in mcr20a_hw_setup()
1005 phy->supported.tx_powers_size = ARRAY_SIZE(mcr20a_powers); in mcr20a_hw_setup()
1006 phy->cca_ed_level = phy->supported.cca_ed_levels[75]; in mcr20a_hw_setup()
1007 phy->transmit_power = phy->supported.tx_powers[0x0F]; in mcr20a_hw_setup()
1013 spi_message_init(&lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1014 lp->tx_buf_msg.context = lp; in mcr20a_setup_tx_spi_messages()
1015 lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete; in mcr20a_setup_tx_spi_messages()
1017 lp->tx_xfer_header.len = 1; in mcr20a_setup_tx_spi_messages()
1018 lp->tx_xfer_header.tx_buf = lp->tx_header; in mcr20a_setup_tx_spi_messages()
1020 lp->tx_xfer_len.len = 1; in mcr20a_setup_tx_spi_messages()
1021 lp->tx_xfer_len.tx_buf = lp->tx_len; in mcr20a_setup_tx_spi_messages()
1023 spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1024 spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1025 spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1031 spi_message_init(&lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1032 lp->reg_msg.context = lp; in mcr20a_setup_rx_spi_messages()
1034 lp->reg_xfer_cmd.len = 1; in mcr20a_setup_rx_spi_messages()
1035 lp->reg_xfer_cmd.tx_buf = lp->reg_cmd; in mcr20a_setup_rx_spi_messages()
1036 lp->reg_xfer_cmd.rx_buf = lp->reg_cmd; in mcr20a_setup_rx_spi_messages()
1038 lp->reg_xfer_data.rx_buf = lp->reg_data; in mcr20a_setup_rx_spi_messages()
1039 lp->reg_xfer_data.tx_buf = lp->reg_data; in mcr20a_setup_rx_spi_messages()
1041 spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1042 spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1044 spi_message_init(&lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1045 lp->rx_buf_msg.context = lp; in mcr20a_setup_rx_spi_messages()
1046 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete; in mcr20a_setup_rx_spi_messages()
1047 lp->rx_xfer_header.len = 1; in mcr20a_setup_rx_spi_messages()
1048 lp->rx_xfer_header.tx_buf = lp->rx_header; in mcr20a_setup_rx_spi_messages()
1049 lp->rx_xfer_header.rx_buf = lp->rx_header; in mcr20a_setup_rx_spi_messages()
1051 lp->rx_xfer_buf.rx_buf = lp->rx_buf; in mcr20a_setup_rx_spi_messages()
1053 lp->rx_xfer_lqi.len = 1; in mcr20a_setup_rx_spi_messages()
1054 lp->rx_xfer_lqi.rx_buf = lp->rx_lqi; in mcr20a_setup_rx_spi_messages()
1056 spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1057 spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1058 spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1064 spi_message_init(&lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1065 lp->irq_msg.context = lp; in mcr20a_setup_irq_spi_messages()
1066 lp->irq_msg.complete = mcr20a_irq_status_complete; in mcr20a_setup_irq_spi_messages()
1067 lp->irq_xfer_header.len = 1; in mcr20a_setup_irq_spi_messages()
1068 lp->irq_xfer_header.tx_buf = lp->irq_header; in mcr20a_setup_irq_spi_messages()
1069 lp->irq_xfer_header.rx_buf = lp->irq_header; in mcr20a_setup_irq_spi_messages()
1071 lp->irq_xfer_data.len = MCR20A_IRQSTS_NUM; in mcr20a_setup_irq_spi_messages()
1072 lp->irq_xfer_data.rx_buf = lp->irq_data; in mcr20a_setup_irq_spi_messages()
1074 spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1075 spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1087 /* Disable Tristate on COCO MISO for SPI reads */ in mcr20a_phy_init()
1088 ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02); in mcr20a_phy_init()
1095 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF); in mcr20a_phy_init()
1100 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2, in mcr20a_phy_init()
1106 /* Disable all timer interrupts */ in mcr20a_phy_init()
1107 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF); in mcr20a_phy_init()
1112 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_phy_init()
1115 /* PHY_CTRL2 : disable all interrupts */ in mcr20a_phy_init()
1116 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF); in mcr20a_phy_init()
1120 /* PHY_CTRL3 : disable all timers and remaining interrupts */ in mcr20a_phy_init()
1121 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3, in mcr20a_phy_init()
1130 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, in mcr20a_phy_init()
1138 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_phy_init()
1150 ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER, in mcr20a_phy_init()
1156 ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites, in mcr20a_phy_init()
1168 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg); in mcr20a_phy_init()
1175 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg); in mcr20a_phy_init()
1185 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg); in mcr20a_phy_init()
1189 /* Set CCA threshold to -75 dBm */ in mcr20a_phy_init()
1190 ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B); in mcr20a_phy_init()
1195 ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05); in mcr20a_phy_init()
1200 ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES, in mcr20a_phy_init()
1206 /* Disable clk_out */ in mcr20a_phy_init()
1207 ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL, in mcr20a_phy_init()
1225 int ret = -ENOMEM; in mcr20a_probe()
1227 dev_dbg(&spi->dev, "%s\n", __func__); in mcr20a_probe()
1229 if (!spi->irq) { in mcr20a_probe()
1230 dev_err(&spi->dev, "no IRQ specified\n"); in mcr20a_probe()
1231 return -EINVAL; in mcr20a_probe()
1234 rst_b = devm_gpiod_get(&spi->dev, "rst_b", GPIOD_OUT_HIGH); in mcr20a_probe()
1236 return dev_err_probe(&spi->dev, PTR_ERR(rst_b), in mcr20a_probe()
1249 dev_crit(&spi->dev, "ieee802154_alloc_hw failed\n"); in mcr20a_probe()
1254 lp = hw->priv; in mcr20a_probe()
1255 lp->hw = hw; in mcr20a_probe()
1256 lp->spi = spi; in mcr20a_probe()
1259 hw->parent = &spi->dev; in mcr20a_probe()
1260 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); in mcr20a_probe()
1263 lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL); in mcr20a_probe()
1265 if (!lp->buf) { in mcr20a_probe()
1266 ret = -ENOMEM; in mcr20a_probe()
1275 lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap); in mcr20a_probe()
1276 if (IS_ERR(lp->regmap_dar)) { in mcr20a_probe()
1277 ret = PTR_ERR(lp->regmap_dar); in mcr20a_probe()
1278 dev_err(&spi->dev, "Failed to allocate dar map: %d\n", in mcr20a_probe()
1283 lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap); in mcr20a_probe()
1284 if (IS_ERR(lp->regmap_iar)) { in mcr20a_probe()
1285 ret = PTR_ERR(lp->regmap_iar); in mcr20a_probe()
1286 dev_err(&spi->dev, "Failed to allocate iar map: %d\n", ret); in mcr20a_probe()
1296 dev_crit(&spi->dev, "mcr20a_phy_init failed\n"); in mcr20a_probe()
1300 irq_type = irq_get_trigger_type(spi->irq); in mcr20a_probe()
1304 ret = devm_request_irq(&spi->dev, spi->irq, mcr20a_irq_isr, in mcr20a_probe()
1305 irq_type | IRQF_NO_AUTOEN, dev_name(&spi->dev), lp); in mcr20a_probe()
1307 dev_err(&spi->dev, "could not request_irq for mcr20a\n"); in mcr20a_probe()
1308 ret = -ENODEV; in mcr20a_probe()
1314 dev_crit(&spi->dev, "ieee802154_register_hw failed\n"); in mcr20a_probe()
1321 ieee802154_free_hw(lp->hw); in mcr20a_probe()
1330 dev_dbg(&spi->dev, "%s\n", __func__); in mcr20a_remove()
1332 ieee802154_unregister_hw(lp->hw); in mcr20a_remove()
1333 ieee802154_free_hw(lp->hw); in mcr20a_remove()