Lines Matching +full:sync +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
118 #define BIT6 1 /* 6 bit/8bit sync */
119 #define LOOPMODE 2 /* SDLC Loop mode */
123 #define NRZ 0 /* NRZ mode */
124 #define NRZI 0x20 /* NRZI mode */
129 /* Write Register 11 (Clock Mode control) */
155 #define SEARCH 0x20 /* Enter search mode */
160 #define SFMM 0xc0 /* Set FM mode */
161 #define SNRZI 0xe0 /* Set NRZI mode */
166 #define SYNCIE 0x10 /* Sync/hunt IE */
177 #define SYNC_HUNT 0x10 /* Sync/hunt */
199 /* Read Register 2 (channel b only) - Interrupt vector */
229 #define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
231 #define FASTDTR 0x10 /* Fast DTR/REQ Mode */