Lines Matching +full:supervisor +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
62 #define B0_MDREG3 0x0030 /* r/w Mode Register 3 */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
79 #define B0_MDREG1 0x006c /* r/w Mode Register 1 */
88 * - completely empty (this is the RAP Block window)
106 /* 0x010a - 0x010b: reserved */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
117 /* 0x011a - 0x011f: reserved */
122 /* 0x012a - 0x012f: reserved */
127 /* 0x013a - 0x013f: reserved */
146 /* 0x016a - 0x017f: reserved */
174 /* 0x0238 - 0x023f: reserved */
189 /* 0x0270 - 0x027c: reserved */
209 /* 0x02b8 - 0x02bc: reserved */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
449 #define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
450 #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
550 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
551 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
585 #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
597 #define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */
598 #define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */
602 #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */
603 #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */
604 #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */
605 #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */
606 #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */
607 #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */
608 #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */
643 #define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */
644 #define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/
645 #define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */
646 #define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a)
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
794 #define MODR1 FM_A(FM_MDREG1) /* mode register 1 */
795 #define MODR2 FM_A(FM_MDREG2) /* mode register 2 */
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */
894 #define TMODE(m) ((m)<<1) /* timer mode */