Lines Matching +full:8 +full:l
40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
95 #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
96 #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
97 #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
98 #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
99 #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
100 #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
101 #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
102 #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
104 #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
105 #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
108 #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
109 #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
110 #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
111 #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
115 #define B2_LD_CRTL 0x0118 /* 8 bit loader control */
116 #define B2_LD_TEST 0x0119 /* 8 bit loader test */
120 #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
121 #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */
125 #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
126 #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */
130 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
131 #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
135 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
136 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
138 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
144 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
145 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
166 #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
167 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
168 #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
169 #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
183 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
184 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
185 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
186 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
201 #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
202 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
203 #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
204 #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
217 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
218 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
219 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
220 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
240 * Bank 8 - 15
250 /* B0_CTRL 8 bit control register */
260 /* B0_DAS 8 Bit control register (DAS) */
269 /* B0_LED 8 Bit LED register */
286 /* B0_TST_CTRL 8 bit test control register */
298 #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
299 #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
300 #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
301 #define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
303 #define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
305 #define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */
306 #define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */
310 #define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */
311 #define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
312 #define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
313 #define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
314 #define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
316 #define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
317 #define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
318 #define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
319 #define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
321 #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
322 #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
323 #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
324 #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
327 #define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
328 #define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
329 #define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
332 #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
333 #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
334 #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
350 #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
351 #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
352 #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
353 #define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
355 #define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
357 #define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */
358 #define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */
359 #define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */
360 #define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
361 #define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
362 #define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
363 #define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
365 #define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
366 #define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
367 #define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
368 #define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
370 #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
371 #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
372 #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
373 #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
376 #define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
377 #define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
378 #define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
381 #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
382 #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
383 #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
392 /* B2_MAC_0 8 bit MAC address Byte 0 */
393 /* B2_MAC_1 8 bit MAC address Byte 1 */
394 /* B2_MAC_2 8 bit MAC address Byte 2 */
395 /* B2_MAC_3 8 bit MAC address Byte 3 */
396 /* B2_MAC_4 8 bit MAC address Byte 4 */
397 /* B2_MAC_5 8 bit MAC address Byte 5 */
398 /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
399 /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
401 /* B2_CONN_TYP 8 bit Connector type */
402 /* B2_PMD_TYP 8 bit PMD type */
406 /* B2_E_0 8 bit EPROM Byte 0 */
407 /* B2_E_1 8 bit EPROM Byte 1 */
408 /* B2_E_2 8 bit EPROM Byte 2 */
409 /* B2_E_3 8 bit EPROM Byte 3 */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
416 /* B2_LD_CRTL 8 bit loader control */
419 /* B2_LD_TEST 8 bit loader test */
427 /* B2_TI_CRTL 8 bit Timer control */
428 /* B2_TI_TEST 8 Bit Timer Test */
431 /* B2_WDOG_CRTL 8 bit Watchdog control */
432 /* B2_WDOG_TEST 8 Bit Watchdog Test */
435 /* B2_RTM_CRTL 8 bit RTM control */
436 /* B2_RTM_TEST 8 Bit RTM Test */
437 /* B2_<TIM>_CRTL 8 bit <TIM> control */
440 /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
441 /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
448 /* B2_<TIM>_TEST 8 Bit <TIM> Test */
455 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
463 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
470 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
480 #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */
483 /* Bit 5.. 8: reserved */
484 #define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */
485 #define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */
486 #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/
487 #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
488 #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
489 #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
490 #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
491 #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
492 #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
493 #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
544 #define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */
545 #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
546 #define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */
547 #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
548 #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
549 #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
550 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
551 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
552 #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
553 #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
554 #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
555 #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
556 #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
557 #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
559 #define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */
560 #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */
561 #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
562 #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
563 #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
573 #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */
574 #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
575 #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */
576 #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/
579 /* Bit 8..15: reserved */
587 #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */
590 /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */
591 /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
592 /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */
593 /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */
642 /* Bit 31..8: reserved */
654 /* Bit 31..8: reserved */
681 #define BMU_STF (1L<<30) /* Start of Frame ? */
682 #define BMU_EOF (1L<<29) /* End of Frame ? */
683 #define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */
684 #define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */
685 #define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */
686 #define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */
687 #define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */
688 #define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */
689 #define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */
721 #define SKFDDI_PSZ 8 /* address PROM size */
851 /* timer access over data bus bit 8..15 */
852 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
853 #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff)