ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Definitions for Xilinx Axi Ethernet device driver.
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
20 #define XAE_HDR_SIZE			14 /* Size of Ethernet header */
21 #define XAE_TRL_SIZE			 4 /* Size of Ethernet trailer (FCS) */
22 #define XAE_MTU			      1500 /* Max MTU of an Ethernet frame */
35 #define XAE_OPTION_JUMBO			BIT(1)
73 /* Axi DMA Register definitions */
126 #define XAXIDMA_DFT_RX_THRESHOLD	1
145 /* Axi Ethernet registers definition */
148 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
161 #define XAE_RCW1_OFFSET		0x00000404 /* Rx Configuration Word 1 */
173 #define XAE_UAW1_OFFSET		0x00000704 /* Unicast address word 1 */
177 #define XAE_AF1_OFFSET		0x00000714 /* Address Filter 1 */
178 #define XAE_AM0_OFFSET		0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET		0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
206 /* Transmit inter-frame gap adjustment value */
209 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
229 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
231 #define XAE_TPID_1_MASK		0xFFFF0000 /* TPID 1 */
233 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
235 #define XAE_TPID_3_MASK		0xFFFF0000 /* TPID 1 */
237 /* Bit masks for Axi Ethernet RCW1 register */
240 /* In-Band FCS enable (FCS not stripped) */
253 /* Bit masks for Axi Ethernet TC register */
256 /* In-Band FCS enable (FCS not generated) */
260 /* Inter-frame gap adjustment enable */
263 /* Bit masks for Axi Ethernet FCC register */
267 /* Bit masks for Axi Ethernet EMMC register */
279 /* Bit masks for Axi Ethernet PHYC register */
282 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
291 /* Bit masks for Axi Ethernet ability register */
298 #define XAE_ABILITY_100M		BIT(1)
301 /* Bit masks for Axi Ethernet MDIO interface MC register */
305 /* Bit masks for Axi Ethernet MDIO interface MCR register */
317 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
320 /* Bit masks for Axi Ethernet UAW1 register */
326 /* Bit masks for Axi Ethernet FMC register */
332 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
334 #define XAE_PHY_TYPE_GMII		1
343 /* Axi Ethernet Synthesis features */
345 #define XAE_FEATURE_PARTIAL_TX_CSUM	BIT(1)
363 /* enum temac_stat - TEMAC statistics counters
419  * struct axidma_bd - Axi Dma buffer descriptor layout
429  * @app1:         MM2S/S2MM User Application Field 1.
437 	u32 next_msb;	/* high 32 bits for IP >= v7.1, reserved on older IP */
439 	u32 phys_msb;	/* for IP >= v7.1, reserved for older IP */
455  * struct skbuf_dma_descriptor - skb for each dma descriptor
463 	struct scatterlist sgl[MAX_SKB_FRAGS + 1];
471  * struct axienet_local - axienet private per device data
479  * @axi_clk:	AXI4-Lite bus clock
480  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
510  * @hw_last_counter: Last-seen value of each statistic counter
518  * @dma_err_task: Work structure to process Axi DMA errors
523  * @eth_irq:	Ethernet core IRQ number
524  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
626  * struct axienet_option - Used to set axi ethernet hardware options
638  * axienet_ior - Memory mapped Axi Ethernet register read
640  * @offset:     Address offset from the base address of Axi Ethernet core
642  * Return: The contents of the Axi Ethernet register
648 	return ioread32(lp->regs + offset);  in axienet_ior()
658 	if (lp->mii_bus)  in axienet_lock_mii()
659 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
664 	if (lp->mii_bus)  in axienet_unlock_mii()
665 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
669  * axienet_iow - Memory mapped Axi Ethernet register write
671  * @offset:     Address offset from the base address of Axi Ethernet core
672  * @value:      Value to be written into the Axi Ethernet register
674  * This function writes the desired value into the corresponding Axi Ethernet
680 	iowrite32(value, lp->regs + offset);  in axienet_iow()
684  * axienet_dma_out32 - Memory mapped Axi DMA register write.
686  * @reg:	Address offset from the base address of the Axi DMA core
687  * @value:	Value to be written into the Axi DMA register
689  * This function writes the desired value into the corresponding Axi DMA
696 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
701  * axienet_dma_out64 - Memory mapped Axi DMA register write.
703  * @reg:	Address offset from the base address of the Axi DMA core
704  * @value:	Value to be written into the Axi DMA register
706  * This function writes the desired value into the corresponding Axi DMA
712 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
718 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()