Lines Matching +full:0 +full:x007fffff
32 #define XAE_OPTION_PROMISC BIT(0)
75 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
76 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
77 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
78 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
80 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
81 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
82 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
83 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
85 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
86 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
88 #define XAXIDMA_SR_HALT_MASK 0x00000001 /* Indicates DMA channel halted */
90 #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
91 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
92 #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
93 #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
94 #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
95 #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
96 #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
97 #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
98 #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
99 #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
100 #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
101 #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
104 #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
105 #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
107 #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
108 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
109 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
110 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
112 #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
113 #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
118 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
119 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
120 #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
121 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
129 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
130 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
131 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
133 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
134 #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
135 #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
136 #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
137 #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
138 #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
139 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
140 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
141 #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
143 #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
146 #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
147 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
149 #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
150 #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
151 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
152 #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
153 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
154 #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
155 #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
156 #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
157 #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
158 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
159 #define XAE_STATS_OFFSET 0x00000200 /* Statistics counters */
160 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
161 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
162 #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
163 #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
164 #define XAE_EMMC_OFFSET 0x00000410 /* MAC speed configuration */
165 #define XAE_PHYC_OFFSET 0x00000414 /* RX Max Frame Configuration */
166 #define XAE_ID_OFFSET 0x000004F8 /* Identification register */
167 #define XAE_ABILITY_OFFSET 0x000004FC /* Ability Register offset */
168 #define XAE_MDIO_MC_OFFSET 0x00000500 /* MDIO Setup */
169 #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MDIO Control */
170 #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MDIO Write Data */
171 #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MDIO Read Data */
172 #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
173 #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
174 #define XAE_FMI_OFFSET 0x00000708 /* Frame Filter Control */
175 #define XAE_FFE_OFFSET 0x0000070C /* Frame Filter Enable */
176 #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
177 #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
181 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
182 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
183 #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
187 #define XAE_RAF_MCSTREJ_MASK 0x00000002
189 #define XAE_RAF_BCSTREJ_MASK 0x00000004
190 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
191 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
192 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
193 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
194 #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
196 #define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000
197 #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
198 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
205 #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
207 #define XAE_IFGP0_IFGP_MASK 0x0000007F
213 #define XAE_INT_HARDACSCMPLT_MASK 0x00000001
215 #define XAE_INT_AUTONEG_MASK 0x00000002
216 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
217 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
218 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
219 #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
220 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
221 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
222 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
223 #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
229 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
230 #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
231 #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
234 #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
235 #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
238 #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
239 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
241 #define XAE_RCW1_FCS_MASK 0x20000000
242 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
243 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
245 #define XAE_RCW1_LT_DIS_MASK 0x02000000
247 #define XAE_RCW1_CL_DIS_MASK 0x01000000
248 /* Pause frame source address bits [47:32]. Bits [31:0] are
251 #define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
254 #define XAE_TC_RST_MASK 0x80000000 /* Reset */
255 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
257 #define XAE_TC_FCS_MASK 0x20000000
258 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
259 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
261 #define XAE_TC_IFG_MASK 0x02000000
264 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
265 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
268 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
269 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
270 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
271 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
272 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
273 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
274 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
275 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
276 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
277 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
280 #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
281 #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
282 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
283 #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
284 #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
285 #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
286 #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
287 #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
288 #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
289 #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
299 #define XAE_ABILITY_10M BIT(0)
302 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
303 #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
306 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
308 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
310 #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
312 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
313 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
314 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
315 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
318 #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
322 * bits [31:0] are stored in register UAW0
324 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
327 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
328 #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
333 #define XAE_PHY_TYPE_MII 0
344 #define XAE_FEATURE_PARTIAL_RX_CSUM BIT(0)
351 #define XAE_NO_CSUM_OFFLOAD 0
353 #define XAE_FULL_CSUM_STATUS_MASK 0x00000038
354 #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
355 #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
360 #define XLNX_MII_STD_SELECT_REG 0x11
361 #define XLNX_MII_STD_SELECT_SGMII BIT(0)
369 STAT_RX_BYTES = 0,
428 * @app0: MM2S/S2MM User Application Field 0.