21 #define reg_rmw(addr, value, mask) \  macro
133 		reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs,  in netcp_xgbe_serdes_cmu_init()
140 		reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs,  in netcp_xgbe_serdes_cmu_init()
154 		reg_rmw(serdes_regs +  in netcp_xgbe_serdes_lane_config()
162 	reg_rmw(serdes_regs + (0x200 * lane) + 0x0380,  in netcp_xgbe_serdes_lane_config()
166 	reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0,  in netcp_xgbe_serdes_lane_config()
175 		reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs,  in netcp_xgbe_serdes_com_enable()
190 	reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff);  in netcp_xgbe_serdes_phyb_rst_clr()
253 		reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24,  in netcp_xgbe_serdes_write_tbus_addr()
270 	reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff);  in netcp_xgbe_serdes_write_tbus_addr()
294 		reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1));  in netcp_xgbe_serdes_reset_cdr()
296 		reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1));  in netcp_xgbe_serdes_reset_cdr()
337 				reg_rmw(sig_detect_reg, VAL_SH(3, 1),  in netcp_xgbe_check_link_status()
378 			reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0),  in netcp_xgbe_check_link_status()
381 			reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0),  in netcp_xgbe_check_link_status()
435 		reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane),  in netcp_xgbe_serdes_setup_cm_c1_c2()
445 	reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN);  in netcp_xgbe_reset_serdes()
449 	reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN);  in netcp_xgbe_reset_serdes()