13 #define XGBE_CTRL_OFFSET		0x0c
14 #define XGBE_SGMII_1_OFFSET		0x0114
15 #define XGBE_SGMII_2_OFFSET		0x0214
18 #define PCSR_CPU_CTRL_OFFSET		0x1fd0
31 #define PHY_A(serdes)			0
40 	{0x0000, 0x00800002, 0x00ff00ff},
41 	{0x0014, 0x00003838, 0x0000ffff},
42 	{0x0060, 0x1c44e438, 0xffffffff},
43 	{0x0064, 0x00c18400, 0x00ffffff},
44 	{0x0068, 0x17078200, 0xffffff00},
45 	{0x006c, 0x00000014, 0x000000ff},
46 	{0x0078, 0x0000c000, 0x0000ff00},
47 	{0x0000, 0x00000003, 0x000000ff},
51 	{0x0c00, 0x00030002, 0x00ff00ff},
52 	{0x0c14, 0x00005252, 0x0000ffff},
53 	{0x0c28, 0x80000000, 0xff000000},
54 	{0x0c2c, 0x000000f6, 0x000000ff},
55 	{0x0c3c, 0x04000405, 0xff00ffff},
56 	{0x0c40, 0xc0800000, 0xffff0000},
57 	{0x0c44, 0x5a202062, 0xffffffff},
58 	{0x0c48, 0x40040424, 0xffffffff},
59 	{0x0c4c, 0x00004002, 0x0000ffff},
60 	{0x0c50, 0x19001c00, 0xff00ff00},
61 	{0x0c54, 0x00002100, 0x0000ff00},
62 	{0x0c58, 0x00000060, 0x000000ff},
63 	{0x0c60, 0x80131e7c, 0xffffffff},
64 	{0x0c64, 0x8400cb02, 0xff00ffff},
65 	{0x0c68, 0x17078200, 0xffffff00},
66 	{0x0c6c, 0x00000016, 0x000000ff},
67 	{0x0c74, 0x00000400, 0x0000ff00},
68 	{0x0c78, 0x0000c000, 0x0000ff00},
69 	{0x0c00, 0x00000003, 0x000000ff},
73 	{0x0204, 0x00000080, 0x000000ff},
74 	{0x0208, 0x0000920d, 0x0000ffff},
75 	{0x0204, 0xfc000000, 0xff000000},
76 	{0x0208, 0x00009104, 0x0000ffff},
77 	{0x0210, 0x1a000000, 0xff000000},
78 	{0x0214, 0x00006b58, 0x00ffffff},
79 	{0x0218, 0x75800084, 0xffff00ff},
80 	{0x022c, 0x00300000, 0x00ff0000},
81 	{0x0230, 0x00003800, 0x0000ff00},
82 	{0x024c, 0x008f0000, 0x00ff0000},
83 	{0x0250, 0x30000000, 0xff000000},
84 	{0x0260, 0x00000002, 0x000000ff},
85 	{0x0264, 0x00000057, 0x000000ff},
86 	{0x0268, 0x00575700, 0x00ffff00},
87 	{0x0278, 0xff000000, 0xff000000},
88 	{0x0280, 0x00500050, 0x00ff00ff},
89 	{0x0284, 0x00001f15, 0x0000ffff},
90 	{0x028c, 0x00006f00, 0x0000ff00},
91 	{0x0294, 0x00000000, 0xffffff00},
92 	{0x0298, 0x00002640, 0xff00ffff},
93 	{0x029c, 0x00000003, 0x000000ff},
94 	{0x02a4, 0x00000f13, 0x0000ffff},
95 	{0x02a8, 0x0001b600, 0x00ffff00},
96 	{0x0380, 0x00000030, 0x000000ff},
97 	{0x03c0, 0x00000200, 0x0000ff00},
98 	{0x03cc, 0x00000018, 0x000000ff},
99 	{0x03cc, 0x00000000, 0x000000ff},
103 	{0x0a00, 0x00000800, 0x0000ff00},
104 	{0x0a84, 0x00000000, 0x000000ff},
105 	{0x0a8c, 0x00130000, 0x00ff0000},
106 	{0x0a90, 0x77a00000, 0xffff0000},
107 	{0x0a94, 0x00007777, 0x0000ffff},
108 	{0x0b08, 0x000f0000, 0xffff0000},
109 	{0x0b0c, 0x000f0000, 0x00ffffff},
110 	{0x0b10, 0xbe000000, 0xff000000},
111 	{0x0b14, 0x000000ff, 0x000000ff},
112 	{0x0b18, 0x00000014, 0x000000ff},
113 	{0x0b5c, 0x981b0000, 0xffff0000},
114 	{0x0b64, 0x00001100, 0x0000ff00},
115 	{0x0b78, 0x00000c00, 0x0000ff00},
116 	{0x0abc, 0xff000000, 0xff000000},
117 	{0x0ac0, 0x0000008b, 0x000000ff},
121 	{0x0208, 0x00000000, 0x00000f00},
122 	{0x0208, 0x00000000, 0x0000001f},
123 	{0x0204, 0x00000000, 0x00040000},
124 	{0x0208, 0x000000a0, 0x000000e0},
132 	for (i = 0; i < ARRAY_SIZE(cfg_phyb_1p25g_156p25mhz_cmu0); i++) {  in netcp_xgbe_serdes_cmu_init()
139 	for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_156p25mhz_cmu1); i++) {  in netcp_xgbe_serdes_cmu_init()
146 /* lane is 0 based */
153 	for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_16bit_lane); i++) {  in netcp_xgbe_serdes_lane_config()
156 				(0x200 * lane),  in netcp_xgbe_serdes_lane_config()
162 	reg_rmw(serdes_regs + (0x200 * lane) + 0x0380,  in netcp_xgbe_serdes_lane_config()
163 		0x00000000, 0x00000010);  in netcp_xgbe_serdes_lane_config()
166 	reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0,  in netcp_xgbe_serdes_lane_config()
167 		0x00000000, 0x00000200);  in netcp_xgbe_serdes_lane_config()
174 	for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_comlane); i++) {  in netcp_xgbe_serdes_com_enable()
185 	writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane));  in netcp_xgbe_serdes_lane_enable()
190 	reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff);  in netcp_xgbe_serdes_phyb_rst_clr()
195 	writel(0x88000000, serdes_regs + 0x1ff4);  in netcp_xgbe_serdes_pll_disable()
201 	writel(0xee000000, serdes_regs + 0x1ff4);  in netcp_xgbe_serdes_pll_enable()
207 	int ret = 0;  in netcp_xgbe_wait_pll_locked()
216 			return 0;  in netcp_xgbe_wait_pll_locked()
232 	writel(0x03, sw_regs + XGBE_CTRL_OFFSET);  in netcp_xgbe_serdes_enable_xgmii_port()
240 		tmp  = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff;  in netcp_xgbe_serdes_read_tbus_val()
241 		tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00);  in netcp_xgbe_serdes_read_tbus_val()
243 		tmp  = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff;  in netcp_xgbe_serdes_read_tbus_val()
253 		reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24,  in netcp_xgbe_serdes_write_tbus_addr()
254 			~0x00ffffff);  in netcp_xgbe_serdes_write_tbus_addr()
270 	reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff);  in netcp_xgbe_serdes_write_tbus_addr()
296 		reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1));  in netcp_xgbe_serdes_reset_cdr()
299 							  1, 0xe);  in netcp_xgbe_serdes_reset_cdr()
311 	void __iomem *pcsr_base = sw_regs + 0x0600;  in netcp_xgbe_check_link_status()
316 	for (i = 0; i < lanes; i++) {  in netcp_xgbe_check_link_status()
318 		loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1;  in netcp_xgbe_check_link_status()
321 		pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80));  in netcp_xgbe_check_link_status()
322 		blk_lock = (pcsr_rx_stat >> 30) & 0x1;  in netcp_xgbe_check_link_status()
323 		blk_errs = (pcsr_rx_stat >> 16) & 0x0ff;  in netcp_xgbe_check_link_status()
326 		sig_detect_reg = serdes_regs + (i * 0x200) + 0x200 + 0x04;  in netcp_xgbe_check_link_status()
329 		if (blk_errs == 0x0ff)  in netcp_xgbe_check_link_status()
330 			blk_lock = 0;  in netcp_xgbe_check_link_status()
333 		case 0:  in netcp_xgbe_check_link_status()
366 				current_state[i] = 0;  in netcp_xgbe_check_link_status()
376 		if (blk_errs > 0) {  in netcp_xgbe_check_link_status()
378 			reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0),  in netcp_xgbe_check_link_status()
379 				MASK_WID_SH(8, 0));  in netcp_xgbe_check_link_status()
381 			reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0),  in netcp_xgbe_check_link_status()
382 				MASK_WID_SH(8, 0));  in netcp_xgbe_check_link_status()
394 	u32 current_state[2] = {0, 0};  in netcp_xgbe_serdes_check_lane()
395 	int retries = 0, link_up;  in netcp_xgbe_serdes_check_lane()
399 		lane_down[0] = 0;  in netcp_xgbe_serdes_check_lane()
400 		lane_down[1] = 0;  in netcp_xgbe_serdes_check_lane()
412 		if (lane_down[0])  in netcp_xgbe_serdes_check_lane()
413 			pr_debug("XGBE: detected link down on lane 0\n");  in netcp_xgbe_serdes_check_lane()
426 	return 0;  in netcp_xgbe_serdes_check_lane()
434 	for (i = 0; i < ARRAY_SIZE(cfg_cm_c1_c2); i++) {  in netcp_xgbe_serdes_setup_cm_c1_c2()
435 		reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane),  in netcp_xgbe_serdes_setup_cm_c1_c2()
449 	reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN);  in netcp_xgbe_reset_serdes()
461 	for (i = 0; i < 2; i++)  in netcp_xgbe_serdes_config()
466 	for (i = 0; i < 2; i++)  in netcp_xgbe_serdes_config()
467 		netcp_xgbe_serdes_setup_cm_c1_c2(serdes_regs, i, 0, 0, 5);  in netcp_xgbe_serdes_config()
470 	for (i = 0; i < 2; i++)  in netcp_xgbe_serdes_config()
487 	/* read COMLANE bits 4:0 */  in netcp_xgbe_serdes_init()
488 	val = readl(serdes_regs + 0xa00);  in netcp_xgbe_serdes_init()
489 	if (val & 0x1f) {  in netcp_xgbe_serdes_init()