22 #define FT1_SLOT_SIZE	0x10	/* bytes */
25 #define FT1_DA0		0x0
26 #define FT1_DA1		0x4
27 #define FT1_DA0_MASK	0x8
28 #define FT1_DA1_MASK	0xc
36 #define FT1_START_MASK		GENMASK(14, 0)
42 	FT1_CFG_TYPE_DISABLED = 0,
49 #define FT1_CFG_MASK(n)		(0x3 << FT1_CFG_SHIFT((n)))
53 #define FT3_SLOT_SIZE	0x20	/* bytes */
56 #define FT3_START		0
57 #define FT3_START_AUTO		0x4
58 #define FT3_START_OFFSET	0x8
59 #define FT3_JUMP_OFFSET		0xc
60 #define FT3_LEN			0x10
61 #define FT3_CFG			0x14
62 #define FT3_T			0x18
63 #define FT3_T_MASK		0x1c
69 #define RX_CLASS_AND_EN		0
70 #define RX_CLASS_OR_EN		0x4
72 #define RX_CLASS_EN_SIZE	0x8	/* bytes */
78 #define RX_CLASS_GATES_SIZE	0x4	/* bytes */
98 #define RX_CLASS_FT_FT3_MATCH_MASK	GENMASK(15, 0)
99 #define RX_CLASS_FT_FT3_MATCH_SHIFT	0
107 	RX_CLASS_SEL_TYPE_OR = 0,
114 #define FT1_CFG_MASK(n)		(0x3 << FT1_CFG_SHIFT((n)))
117 #define RX_CLASS_SEL_MASK(n)	(0x3 << RX_CLASS_SEL_SHIFT((n)))
119 #define ICSSG_CFG_OFFSET	0
120 #define MAC_INTERFACE_0		0x18
121 #define MAC_INTERFACE_1		0x1c
155 		0x8,
156 		0xc,
157 		0x80,
158 		0x84,
159 		0x88,
160 		0x108,
161 		0x308,
162 		0x408,
163 		0x40c,
164 		0x48c,
165 		0x490,
166 		0x494,
167 		0x4d4,
168 		0x4e4,
169 		0x504,
170 		0x508,
171 		0x50c,
172 		0x54c,
173 		0x63c,
174 		0x640,
175 		0x644,
176 		0x648,
180 		0x10,
181 		0x14,
182 		0x64c,
183 		0x650,
184 		0x654,
185 		0x6d4,
186 		0x8d4,
187 		0x9d4,
188 		0x9d8,
189 		0xa58,
190 		0xa5c,
191 		0xa60,
192 		0xaa0,
193 		0xab0,
194 		0xad0,
195 		0xad4,
196 		0xad8,
197 		0xb18,
198 		0xc08,
199 		0xc0c,
200 		0xc10,
201 		0xc14,
221 	regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 |  in rx_class_ft1_set_da()
233 	regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 |  in rx_class_ft1_set_da_mask()
289 	regmap_write(miig_rt, MAC_INTERFACE_0, (u32)(mac[0] | mac[1] << 8 |  in icssg_class_set_host_mac_addr()
297 	regmap_write(miig_rt, offs[slice].mac0, (u32)(mac[0] | mac[1] << 8 |  in icssg_class_set_mac_addr()
316 	for (i = 0; i < ICSSG_NUM_CLASSIFIERS_IN_USE; i++) {  in icssg_class_ft1_add_mcast()
333 	for (n = 0; n < ICSSG_NUM_CLASSIFIERS; n++) {  in icssg_class_disable()
334 		/* AND_EN = 0 */  in icssg_class_disable()
335 		rx_class_set_and(miig_rt, slice, n, 0);  in icssg_class_disable()
336 		/* OR_EN = 0 */  in icssg_class_disable()
337 		rx_class_set_or(miig_rt, slice, n, 0);  in icssg_class_disable()
353 	for (n = 0; n < ICSSG_NUM_FT1_SLOTS; n++) {  in icssg_class_disable()
354 		const u8 addr[] = { 0, 0, 0, 0, 0, 0, };  in icssg_class_disable()
363 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_disable()
378 	for (n = 0; n < num_classifiers; n++) {  in icssg_class_default()
394 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_default()
407 	for (n = 0; n < ICSSG_NUM_CLASSIFIERS_IN_USE; n++) {  in icssg_class_promiscuous_sr1()
420 	u8 mask_addr[6] = { 0, 0, 0, 0, 0, 0xff };  in icssg_class_add_mcast_sr1()
424 	rx_class_ft1_set_start_len(miig_rt, slice, 0, 6);  in icssg_class_add_mcast_sr1()
428 	 *			      (224.0.0.0 - 224.0.0.255  (224.0.0/24))  in icssg_class_add_mcast_sr1()
430 	icssg_class_ft1_add_mcast(miig_rt, slice, 0,  in icssg_class_add_mcast_sr1()
434 	mask_addr[5] = 0;  in icssg_class_add_mcast_sr1()
462 	const u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, };  in icssg_ft1_set_mac_addr()
465 	rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr);  in icssg_ft1_set_mac_addr()
466 	rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr);  in icssg_ft1_set_mac_addr()
467 	rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ);  in icssg_ft1_set_mac_addr()