62 int icss_iep_get_count_hi(struct icss_iep *iep)  in icss_iep_get_count_hi()  argument
66 	if (iep && (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT))  in icss_iep_get_count_hi()
67 		val = readl(iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG1]);  in icss_iep_get_count_hi()
79 int icss_iep_get_count_low(struct icss_iep *iep)  in icss_iep_get_count_low()  argument
83 	if (iep)  in icss_iep_get_count_low()
84 		val = readl(iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG0]);  in icss_iep_get_count_low()
96 int icss_iep_get_ptp_clock_idx(struct icss_iep *iep)  in icss_iep_get_ptp_clock_idx()  argument
98 	if (!iep || !iep->ptp_clock)  in icss_iep_get_ptp_clock_idx()
100 	return ptp_clock_index(iep->ptp_clock);  in icss_iep_get_ptp_clock_idx()
104 static void icss_iep_set_counter(struct icss_iep *iep, u64 ns)  in icss_iep_set_counter()  argument
106 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_set_counter()
107 		writel(upper_32_bits(ns), iep->base +  in icss_iep_set_counter()
108 		       iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG1]);  in icss_iep_set_counter()
109 	writel(lower_32_bits(ns), iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG0]);  in icss_iep_set_counter()
112 static void icss_iep_update_to_next_boundary(struct icss_iep *iep, u64 start_ns);
122 static void icss_iep_settime(struct icss_iep *iep, u64 ns)  in icss_iep_settime()  argument
124 	if (iep->ops && iep->ops->settime) {  in icss_iep_settime()
125 		iep->ops->settime(iep->clockops_data, ns);  in icss_iep_settime()
129 	if (iep->pps_enabled || iep->perout_enabled)  in icss_iep_settime()
130 		writel(0, iep->base + iep->plat_data->reg_offs[ICSS_IEP_SYNC_CTRL_REG]);  in icss_iep_settime()
132 	icss_iep_set_counter(iep, ns);  in icss_iep_settime()
134 	if (iep->pps_enabled || iep->perout_enabled) {  in icss_iep_settime()
135 		icss_iep_update_to_next_boundary(iep, ns);  in icss_iep_settime()
137 		       iep->base + iep->plat_data->reg_offs[ICSS_IEP_SYNC_CTRL_REG]);  in icss_iep_settime()
151 static u64 icss_iep_gettime(struct icss_iep *iep,  in icss_iep_gettime()  argument
157 	if (iep->ops && iep->ops->gettime)  in icss_iep_gettime()
158 		return iep->ops->gettime(iep->clockops_data, sts);  in icss_iep_gettime()
165 	ts_lo = readl(iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG0]);  in icss_iep_gettime()
167 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_gettime()
168 		ts_hi = readl(iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG1]);  in icss_iep_gettime()
175 static void icss_iep_enable(struct icss_iep *iep)  in icss_iep_enable()  argument
177 	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,  in icss_iep_enable()
182 static void icss_iep_disable(struct icss_iep *iep)  in icss_iep_disable()  argument
184 	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,  in icss_iep_disable()
189 static void icss_iep_enable_shadow_mode(struct icss_iep *iep)  in icss_iep_enable_shadow_mode()  argument
194 	cycle_time = iep->cycle_time_ns - iep->def_inc;  in icss_iep_enable_shadow_mode()
196 	icss_iep_disable(iep);  in icss_iep_enable_shadow_mode()
199 	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_enable_shadow_mode()
203 	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_enable_shadow_mode()
207 	icss_iep_set_counter(iep, 0);  in icss_iep_enable_shadow_mode()
210 	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_STATUS_REG,  in icss_iep_enable_shadow_mode()
216 		regmap_update_bits(iep->map, ICSS_IEP_CMP_STAT_REG,  in icss_iep_enable_shadow_mode()
221 	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_enable_shadow_mode()
225 	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_enable_shadow_mode()
230 	regmap_write(iep->map, ICSS_IEP_CMP0_REG0, cycle_time);  in icss_iep_enable_shadow_mode()
231 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_enable_shadow_mode()
232 		regmap_write(iep->map, ICSS_IEP_CMP0_REG1, cycle_time);  in icss_iep_enable_shadow_mode()
234 	icss_iep_set_counter(iep, 0);  in icss_iep_enable_shadow_mode()
235 	icss_iep_enable(iep);  in icss_iep_enable_shadow_mode()
238 static void icss_iep_set_default_inc(struct icss_iep *iep, u8 def_inc)  in icss_iep_set_default_inc()  argument
240 	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,  in icss_iep_set_default_inc()
245 static void icss_iep_set_compensation_inc(struct icss_iep *iep, u16 compen_inc)  in icss_iep_set_compensation_inc()  argument
247 	struct device *dev = regmap_get_device(iep->map);  in icss_iep_set_compensation_inc()
255 	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,  in icss_iep_set_compensation_inc()
260 static void icss_iep_set_compensation_count(struct icss_iep *iep,  in icss_iep_set_compensation_count()  argument
263 	struct device *dev = regmap_get_device(iep->map);  in icss_iep_set_compensation_count()
271 	regmap_write(iep->map, ICSS_IEP_COMPEN_REG, compen_count);  in icss_iep_set_compensation_count()
274 static void icss_iep_set_slow_compensation_count(struct icss_iep *iep,  in icss_iep_set_slow_compensation_count()  argument
277 	regmap_write(iep->map, ICSS_IEP_SLOW_COMPEN_REG, compen_count);  in icss_iep_set_slow_compensation_count()
283 	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);  in icss_iep_ptp_adjfine()  local
288 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_ptp_adjfine()
306 	if (iep->cycle_time_ns)  in icss_iep_ptp_adjfine()
307 		iep->slow_cmp_inc = iep->clk_tick_time;	/* 4ns adj per cycle */  in icss_iep_ptp_adjfine()
309 		iep->slow_cmp_inc = 1;	/* 1ns adjust per cycle */  in icss_iep_ptp_adjfine()
312 		iep->slow_cmp_inc = -iep->slow_cmp_inc;  in icss_iep_ptp_adjfine()
320 	if (!iep->cycle_time_ns)  in icss_iep_ptp_adjfine()
321 		cyc_count /= iep->clk_tick_time;  in icss_iep_ptp_adjfine()
322 	iep->slow_cmp_count = cyc_count;  in icss_iep_ptp_adjfine()
325 	cmp_inc = iep->clk_tick_time + iep->slow_cmp_inc;  in icss_iep_ptp_adjfine()
326 	icss_iep_set_compensation_inc(iep, cmp_inc);  in icss_iep_ptp_adjfine()
327 	icss_iep_set_slow_compensation_count(iep, iep->slow_cmp_count);  in icss_iep_ptp_adjfine()
329 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_ptp_adjfine()
336 	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);  in icss_iep_ptp_adjtime()  local
339 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_ptp_adjtime()
340 	if (iep->ops && iep->ops->adjtime) {  in icss_iep_ptp_adjtime()
341 		iep->ops->adjtime(iep->clockops_data, delta);  in icss_iep_ptp_adjtime()
343 		ns = icss_iep_gettime(iep, NULL);  in icss_iep_ptp_adjtime()
345 		icss_iep_settime(iep, ns);  in icss_iep_ptp_adjtime()
347 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_ptp_adjtime()
356 	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);  in icss_iep_ptp_gettimeex()  local
359 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_ptp_gettimeex()
360 	ns = icss_iep_gettime(iep, sts);  in icss_iep_ptp_gettimeex()
362 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_ptp_gettimeex()
370 	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);  in icss_iep_ptp_settime()  local
373 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_ptp_settime()
375 	icss_iep_settime(iep, ns);  in icss_iep_ptp_settime()
376 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_ptp_settime()
381 static void icss_iep_update_to_next_boundary(struct icss_iep *iep, u64 start_ns)  in icss_iep_update_to_next_boundary()  argument
386 	ns = icss_iep_gettime(iep, NULL);  in icss_iep_update_to_next_boundary()
389 	p_ns = iep->period;  in icss_iep_update_to_next_boundary()
398 	regmap_write(iep->map, ICSS_IEP_CMP1_REG0, lower_32_bits(start_ns));  in icss_iep_update_to_next_boundary()
399 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_update_to_next_boundary()
400 		regmap_write(iep->map, ICSS_IEP_CMP1_REG1, upper_32_bits(start_ns));  in icss_iep_update_to_next_boundary()
403 static int icss_iep_perout_enable_hw(struct icss_iep *iep,  in icss_iep_perout_enable_hw()  argument
409 	if (iep->ops && iep->ops->perout_enable) {  in icss_iep_perout_enable_hw()
410 		ret = iep->ops->perout_enable(iep->clockops_data, req, on, &cmp);  in icss_iep_perout_enable_hw()
416 			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, lower_32_bits(cmp));  in icss_iep_perout_enable_hw()
417 			if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_perout_enable_hw()
418 				regmap_write(iep->map, ICSS_IEP_CMP1_REG1, upper_32_bits(cmp));  in icss_iep_perout_enable_hw()
420 			regmap_write(iep->map, ICSS_IEP_SYNC_PWIDTH_REG, 1000000);  in icss_iep_perout_enable_hw()
421 			regmap_write(iep->map, ICSS_IEP_SYNC0_PERIOD_REG, 0);  in icss_iep_perout_enable_hw()
422 			regmap_write(iep->map, ICSS_IEP_SYNC_START_REG, 0);  in icss_iep_perout_enable_hw()
423 			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG, 0); /* one-shot mode */  in icss_iep_perout_enable_hw()
425 			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_perout_enable_hw()
429 			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_perout_enable_hw()
433 			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, 0);  in icss_iep_perout_enable_hw()
434 			if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_perout_enable_hw()
435 				regmap_write(iep->map, ICSS_IEP_CMP1_REG1, 0);  in icss_iep_perout_enable_hw()
441 			iep->period = ((u64)req->period.sec * NSEC_PER_SEC) +  in icss_iep_perout_enable_hw()
445 			icss_iep_update_to_next_boundary(iep, start_ns);  in icss_iep_perout_enable_hw()
448 			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG,  in icss_iep_perout_enable_hw()
451 			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_perout_enable_hw()
455 			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,  in icss_iep_perout_enable_hw()
459 			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, 0);  in icss_iep_perout_enable_hw()
460 			if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_perout_enable_hw()
461 				regmap_write(iep->map, ICSS_IEP_CMP1_REG1, 0);  in icss_iep_perout_enable_hw()
464 			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG, 0);  in icss_iep_perout_enable_hw()
471 static int icss_iep_perout_enable(struct icss_iep *iep,  in icss_iep_perout_enable()  argument
476 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_perout_enable()
478 	if (iep->pps_enabled) {  in icss_iep_perout_enable()
483 	if (iep->perout_enabled == !!on)  in icss_iep_perout_enable()
486 	ret = icss_iep_perout_enable_hw(iep, req, on);  in icss_iep_perout_enable()
488 		iep->perout_enabled = !!on;  in icss_iep_perout_enable()
491 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_perout_enable()
498 	struct icss_iep *iep = container_of(work, struct icss_iep, work);  in icss_iep_cap_cmp_work()  local
499 	const u32 *reg_offs = iep->plat_data->reg_offs;  in icss_iep_cap_cmp_work()
504 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_cap_cmp_work()
506 	ns = readl(iep->base + reg_offs[ICSS_IEP_CMP1_REG0]);  in icss_iep_cap_cmp_work()
507 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT) {  in icss_iep_cap_cmp_work()
508 		val = readl(iep->base + reg_offs[ICSS_IEP_CMP1_REG1]);  in icss_iep_cap_cmp_work()
512 	ns_next = ns + iep->period;  in icss_iep_cap_cmp_work()
514 	       iep->base + reg_offs[ICSS_IEP_CMP1_REG0]);  in icss_iep_cap_cmp_work()
515 	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)  in icss_iep_cap_cmp_work()
517 		       iep->base + reg_offs[ICSS_IEP_CMP1_REG1]);  in icss_iep_cap_cmp_work()
522 	ptp_clock_event(iep->ptp_clock, &pevent);  in icss_iep_cap_cmp_work()
523 	dev_dbg(iep->dev, "IEP:pps ts: %llu next:%llu:\n", ns, ns_next);  in icss_iep_cap_cmp_work()
525 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_cap_cmp_work()
530 	struct icss_iep *iep = (struct icss_iep *)dev_id;  in icss_iep_cap_cmp_irq()  local
531 	const u32 *reg_offs = iep->plat_data->reg_offs;  in icss_iep_cap_cmp_irq()
534 	val = readl(iep->base + reg_offs[ICSS_IEP_CMP_STAT_REG]);  in icss_iep_cap_cmp_irq()
538 		writel(BIT(1), iep->base + reg_offs[ICSS_IEP_CMP_STAT_REG]);  in icss_iep_cap_cmp_irq()
539 		if (iep->pps_enabled || iep->perout_enabled)  in icss_iep_cap_cmp_irq()
540 			schedule_work(&iep->work);  in icss_iep_cap_cmp_irq()
547 static int icss_iep_pps_enable(struct icss_iep *iep, int on)  in icss_iep_pps_enable()  argument
554 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_pps_enable()
556 	if (iep->perout_enabled) {  in icss_iep_pps_enable()
561 	if (iep->pps_enabled == !!on)  in icss_iep_pps_enable()
566 		ns = icss_iep_gettime(iep, NULL);  in icss_iep_pps_enable()
572 		ret = icss_iep_perout_enable_hw(iep, &rq.perout, on);  in icss_iep_pps_enable()
574 		ret = icss_iep_perout_enable_hw(iep, &rq.perout, on);  in icss_iep_pps_enable()
575 		if (iep->cap_cmp_irq)  in icss_iep_pps_enable()
576 			cancel_work_sync(&iep->work);  in icss_iep_pps_enable()
580 		iep->pps_enabled = !!on;  in icss_iep_pps_enable()
583 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_pps_enable()
588 static int icss_iep_extts_enable(struct icss_iep *iep, u32 index, int on)  in icss_iep_extts_enable()  argument
592 	mutex_lock(&iep->ptp_clk_mutex);  in icss_iep_extts_enable()
594 	if (iep->ops && iep->ops->extts_enable) {  in icss_iep_extts_enable()
595 		ret = iep->ops->extts_enable(iep->clockops_data, index, on);  in icss_iep_extts_enable()
599 	if (((iep->latch_enable & BIT(index)) >> index) == on)  in icss_iep_extts_enable()
602 	regmap_read(iep->map, ICSS_IEP_CAPTURE_CFG_REG, &val);  in icss_iep_extts_enable()
606 		iep->latch_enable |= BIT(index);  in icss_iep_extts_enable()
609 		iep->latch_enable &= ~BIT(index);  in icss_iep_extts_enable()
611 	regmap_write(iep->map, ICSS_IEP_CAPTURE_CFG_REG, val);  in icss_iep_extts_enable()
614 	mutex_unlock(&iep->ptp_clk_mutex);  in icss_iep_extts_enable()
622 	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);  in icss_iep_ptp_enable()  local
626 		return icss_iep_perout_enable(iep, &rq->perout, on);  in icss_iep_ptp_enable()
628 		return icss_iep_pps_enable(iep, on);  in icss_iep_ptp_enable()
630 		return icss_iep_extts_enable(iep, rq->extts.index, on);  in icss_iep_ptp_enable()
653 	struct icss_iep *iep;  in icss_iep_get_idx()  local
666 	iep = platform_get_drvdata(pdev);  in icss_iep_get_idx()
667 	if (!iep)  in icss_iep_get_idx()
670 	device_lock(iep->dev);  in icss_iep_get_idx()
671 	if (iep->client_np) {  in icss_iep_get_idx()
672 		device_unlock(iep->dev);  in icss_iep_get_idx()
673 		dev_err(iep->dev, "IEP is already acquired by %s",  in icss_iep_get_idx()
674 			iep->client_np->name);  in icss_iep_get_idx()
677 	iep->client_np = np;  in icss_iep_get_idx()
678 	device_unlock(iep->dev);  in icss_iep_get_idx()
679 	get_device(iep->dev);  in icss_iep_get_idx()
681 	return iep;  in icss_iep_get_idx()
691 void icss_iep_put(struct icss_iep *iep)  in icss_iep_put()  argument
693 	device_lock(iep->dev);  in icss_iep_put()
694 	iep->client_np = NULL;  in icss_iep_put()
695 	device_unlock(iep->dev);  in icss_iep_put()
696 	put_device(iep->dev);  in icss_iep_put()
700 void icss_iep_init_fw(struct icss_iep *iep)  in icss_iep_init_fw()  argument
703 	iep->clk_tick_time = iep->def_inc;  in icss_iep_init_fw()
704 	iep->cycle_time_ns = 0;  in icss_iep_init_fw()
705 	iep->ops = NULL;  in icss_iep_init_fw()
706 	iep->clockops_data = NULL;  in icss_iep_init_fw()
707 	icss_iep_set_default_inc(iep, iep->def_inc);  in icss_iep_init_fw()
708 	icss_iep_set_compensation_inc(iep, iep->def_inc);  in icss_iep_init_fw()
709 	icss_iep_set_compensation_count(iep, 0);  in icss_iep_init_fw()
710 	regmap_write(iep->map, ICSS_IEP_SYNC_PWIDTH_REG, iep->refclk_freq / 10); /* 100 ms pulse */  in icss_iep_init_fw()
711 	regmap_write(iep->map, ICSS_IEP_SYNC0_PERIOD_REG, 0);  in icss_iep_init_fw()
712 	if (iep->plat_data->flags & ICSS_IEP_SLOW_COMPEN_REG_SUPPORT)  in icss_iep_init_fw()
713 		icss_iep_set_slow_compensation_count(iep, 0);  in icss_iep_init_fw()
715 	icss_iep_enable(iep);  in icss_iep_init_fw()
716 	icss_iep_settime(iep, 0);  in icss_iep_init_fw()
720 void icss_iep_exit_fw(struct icss_iep *iep)  in icss_iep_exit_fw()  argument
722 	icss_iep_disable(iep);  in icss_iep_exit_fw()
726 int icss_iep_init(struct icss_iep *iep, const struct icss_iep_clockops *clkops,  in icss_iep_init()  argument
731 	iep->cycle_time_ns = cycle_time_ns;  in icss_iep_init()
732 	iep->clk_tick_time = iep->def_inc;  in icss_iep_init()
733 	iep->ops = clkops;  in icss_iep_init()
734 	iep->clockops_data = clockops_data;  in icss_iep_init()
735 	icss_iep_set_default_inc(iep, iep->def_inc);  in icss_iep_init()
736 	icss_iep_set_compensation_inc(iep, iep->def_inc);  in icss_iep_init()
737 	icss_iep_set_compensation_count(iep, 0);  in icss_iep_init()
738 	regmap_write(iep->map, ICSS_IEP_SYNC_PWIDTH_REG, iep->refclk_freq / 10); /* 100 ms pulse */  in icss_iep_init()
739 	regmap_write(iep->map, ICSS_IEP_SYNC0_PERIOD_REG, 0);  in icss_iep_init()
740 	if (iep->plat_data->flags & ICSS_IEP_SLOW_COMPEN_REG_SUPPORT)  in icss_iep_init()
741 		icss_iep_set_slow_compensation_count(iep, 0);  in icss_iep_init()
743 	if (!(iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT) ||  in icss_iep_init()
744 	    !(iep->plat_data->flags & ICSS_IEP_SLOW_COMPEN_REG_SUPPORT))  in icss_iep_init()
747 	if (iep->ops && iep->ops->perout_enable) {  in icss_iep_init()
748 		iep->ptp_info.n_per_out = 1;  in icss_iep_init()
749 		iep->ptp_info.pps = 1;  in icss_iep_init()
750 	} else if (iep->cap_cmp_irq) {  in icss_iep_init()
751 		iep->ptp_info.pps = 1;  in icss_iep_init()
754 	if (iep->ops && iep->ops->extts_enable)  in icss_iep_init()
755 		iep->ptp_info.n_ext_ts = 2;  in icss_iep_init()
759 		icss_iep_enable_shadow_mode(iep);  in icss_iep_init()
761 		icss_iep_enable(iep);  in icss_iep_init()
762 	icss_iep_settime(iep, ktime_get_real_ns());  in icss_iep_init()
764 	iep->ptp_clock = ptp_clock_register(&iep->ptp_info, iep->dev);  in icss_iep_init()
765 	if (IS_ERR(iep->ptp_clock)) {  in icss_iep_init()
766 		ret = PTR_ERR(iep->ptp_clock);  in icss_iep_init()
767 		iep->ptp_clock = NULL;  in icss_iep_init()
768 		dev_err(iep->dev, "Failed to register ptp clk %d\n", ret);  in icss_iep_init()
775 int icss_iep_exit(struct icss_iep *iep)  in icss_iep_exit()  argument
777 	if (iep->ptp_clock) {  in icss_iep_exit()
778 		ptp_clock_unregister(iep->ptp_clock);  in icss_iep_exit()
779 		iep->ptp_clock = NULL;  in icss_iep_exit()
781 	icss_iep_disable(iep);  in icss_iep_exit()
790 	struct icss_iep *iep;  in icss_iep_probe()  local
794 	iep = devm_kzalloc(dev, sizeof(*iep), GFP_KERNEL);  in icss_iep_probe()
795 	if (!iep)  in icss_iep_probe()
798 	iep->dev = dev;  in icss_iep_probe()
799 	iep->base = devm_platform_ioremap_resource(pdev, 0);  in icss_iep_probe()
800 	if (IS_ERR(iep->base))  in icss_iep_probe()
809 				       IRQF_TRIGGER_HIGH, "iep_cap_cmp", iep);  in icss_iep_probe()
811 			dev_info(iep->dev, "cap_cmp irq request failed: %x\n",  in icss_iep_probe()
814 			iep->cap_cmp_irq = irq;  in icss_iep_probe()
815 			INIT_WORK(&iep->work, icss_iep_cap_cmp_work);  in icss_iep_probe()
823 	iep->refclk_freq = clk_get_rate(iep_clk);  in icss_iep_probe()
825 	iep->def_inc = NSEC_PER_SEC / iep->refclk_freq;	/* ns per clock tick */  in icss_iep_probe()
826 	if (iep->def_inc > IEP_MAX_DEF_INC) {  in icss_iep_probe()
828 			iep->def_inc);  in icss_iep_probe()
832 	iep->plat_data = device_get_match_data(dev);  in icss_iep_probe()
833 	if (!iep->plat_data)  in icss_iep_probe()
836 	iep->map = devm_regmap_init(dev, NULL, iep, iep->plat_data->config);  in icss_iep_probe()
837 	if (IS_ERR(iep->map)) {  in icss_iep_probe()
839 			PTR_ERR(iep->map));  in icss_iep_probe()
840 		return PTR_ERR(iep->map);  in icss_iep_probe()
843 	iep->ptp_info = icss_iep_ptp_info;  in icss_iep_probe()
844 	mutex_init(&iep->ptp_clk_mutex);  in icss_iep_probe()
845 	dev_set_drvdata(dev, iep);  in icss_iep_probe()
846 	icss_iep_disable(iep);  in icss_iep_probe()
866 	struct icss_iep *iep = context;  in icss_iep_regmap_write()  local
868 	writel(val, iep->base + iep->plat_data->reg_offs[reg]);  in icss_iep_regmap_write()
876 	struct icss_iep *iep = context;  in icss_iep_regmap_read()  local
878 	*val = readl(iep->base + iep->plat_data->reg_offs[reg]);  in icss_iep_regmap_read()