341 	writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);  in cpsw_ale_read()
344 		ale_entry[i] = readl_relaxed(ale->params.ale_regs +  in cpsw_ale_read()
357 		writel_relaxed(ale_entry[i], ale->params.ale_regs +  in cpsw_ale_write()
360 	writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +  in cpsw_ale_write()
614 	writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));  in cpsw_ale_set_vlan_mcast()
619 	writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));  in cpsw_ale_set_vlan_mcast()
857 	unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));  in cpsw_ale_vlan_set_unreg_mcast_idx()
864 	writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));  in cpsw_ale_vlan_set_unreg_mcast_idx()
1146 	tmp = readl_relaxed(ale->params.ale_regs + offset);  in cpsw_ale_control_set()
1148 	writel_relaxed(tmp, ale->params.ale_regs + offset);  in cpsw_ale_control_set()
1172 	tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;  in cpsw_ale_control_get()
1245 	writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);  in cpsw_ale_hw_aging_timer_start()
1250 	writel(0, ale->params.ale_regs + ALE_AGING_TIMER);  in cpsw_ale_hw_aging_timer_stop()
1296 	writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE);  in cpsw_ale_start()
1520 	ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs,  in cpsw_ale_create()
1645 	writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);  in cpsw_ale_policer_read_idx()
1653 	writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);  in cpsw_ale_policer_write_idx()