Lines Matching +full:0 +full:x000fc000
15 #define GREG_SWRESET 0x000UL /* Software Reset */
16 #define GREG_CFG 0x004UL /* Config Register */
17 #define GREG_STAT 0x100UL /* Status */
18 #define GREG_IMASK 0x104UL /* Interrupt Mask */
19 #define GREG_REG_SIZE 0x108UL
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
29 #define GREG_CFG_BURST32 0x01
30 #define GREG_CFG_BURST64 0x02
31 #define GREG_CFG_64BIT 0x04
32 #define GREG_CFG_PARITY 0x08
33 #define GREG_CFG_RESV 0x10
36 #define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */
37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
43 #define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */
44 #define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
51 #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
58 #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
59 #define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
60 #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
61 #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
62 #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
63 #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
64 #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
65 #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
66 #define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */
67 #define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */
70 #define GREG_STAT_ERRORS 0xfc7efefc
73 #define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
75 #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
76 #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
77 #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
79 #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
80 #define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */
81 #define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
82 #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
83 #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
84 #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
85 #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
86 #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
87 #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
88 #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
89 #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
90 #define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */
91 #define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */
92 #define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */
93 #define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */
94 #define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */
95 #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
96 #define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
97 #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
98 #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
99 #define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */
100 #define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */
101 #define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */
102 #define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */
103 #define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */
104 #define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */
107 #define ETX_PENDING 0x00UL /* Transmit pending/wakeup register */
108 #define ETX_CFG 0x04UL /* Transmit config register */
109 #define ETX_RING 0x08UL /* Transmit ring pointer */
110 #define ETX_BBASE 0x0cUL /* Transmit buffer base */
111 #define ETX_BDISP 0x10UL /* Transmit buffer displacement */
112 #define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */
113 #define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */
114 #define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */
115 #define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */
116 #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
117 #define ETX_SMACHINE 0x28UL /* Transmitter state machine */
118 #define ETX_RSIZE 0x2cUL /* Ring descriptor size */
119 #define ETX_BPTR 0x30UL /* Transmit data buffer ptr */
120 #define ETX_REG_SIZE 0x34UL
123 #define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
126 #define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */
127 #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
128 #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
129 #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
134 #define ERX_CFG 0x00UL /* Receiver config register */
135 #define ERX_RING 0x04UL /* Receiver ring ptr */
136 #define ERX_BPTR 0x08UL /* Receiver buffer ptr */
137 #define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */
138 #define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */
139 #define ERX_FIFORPTR 0x14UL /* FIFO read ptr */
140 #define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */
141 #define ERX_SMACHINE 0x1cUL /* Receiver state machine */
142 #define ERX_REG_SIZE 0x20UL
145 #define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */
146 #define ERX_CFG_RESV1 0x00000006 /* Unused... */
147 #define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */
148 #define ERX_CFG_RESV2 0x000001c0 /* Unused... */
149 #define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */
150 #define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */
151 #define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */
152 #define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */
153 #define ERX_CFG_RESV3 0x0000f800 /* Unused... */
154 #define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start,
158 #define BMAC_XIFCFG 0x0000UL /* XIF config register */
159 /* 0x4-->0x204, reserved */
160 #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
161 #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
162 #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
163 #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
164 #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
165 #define BMAC_STIME 0x21cUL /* Transmit slot time */
166 #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
167 #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
168 #define BMAC_TXSDELIM 0x228UL /* Transmit delimiter */
169 #define BMAC_JSIZE 0x22cUL /* Jam size */
170 #define BMAC_TXMAX 0x230UL /* Transmit max pkt size */
171 #define BMAC_TXMIN 0x234UL /* Transmit min pkt size */
172 #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
173 #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
174 #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
175 #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
176 #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
177 #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
178 #define BMAC_RSEED 0x250UL /* Transmit random number seed */
179 #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
180 /* 0x258-->0x304, reserved */
181 #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
182 #define BMAC_RXCFG 0x30cUL /* Receiver config register */
183 #define BMAC_RXMAX 0x310UL /* Receive max pkt size */
184 #define BMAC_RXMIN 0x314UL /* Receive min pkt size */
185 #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
186 #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
187 #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
188 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
189 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
190 #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
191 #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
192 #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
193 #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
194 /* 0x33c, reserved */
195 #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
196 #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
197 #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
198 #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
199 #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
200 #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
201 #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
202 #define BMAC_AFMASK 0x35cUL /* Address filter mask */
203 #define BMAC_REG_SIZE 0x360UL
206 #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
207 #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
208 #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
209 #define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
210 #define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */
211 #define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */
212 #define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */
213 #define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
216 #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
217 #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
218 #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
219 #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
220 #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
221 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
222 #define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
225 #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
226 #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
227 #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */
228 #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
229 #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
230 #define BIGMAC_RXCFG_REJME 0x00000200 /* Reject packets addressed to me */
231 #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
232 #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
233 #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
236 #define TCVR_BBCLOCK 0x00UL /* Bit bang clock register */
237 #define TCVR_BBDATA 0x04UL /* Bit bang data register */
238 #define TCVR_BBOENAB 0x08UL /* Bit bang output enable */
239 #define TCVR_FRAME 0x0cUL /* Frame control/data register */
240 #define TCVR_CFG 0x10UL /* MIF config register */
241 #define TCVR_IMASK 0x14UL /* MIF interrupt mask */
242 #define TCVR_STATUS 0x18UL /* MIF status */
243 #define TCVR_SMACHINE 0x1cUL /* MIF state machine */
244 #define TCVR_REG_SIZE 0x20UL
247 #define FRAME_WRITE 0x50020000
248 #define FRAME_READ 0x60020000
251 #define TCV_CFG_PSELECT 0x00000001 /* Select PHY */
252 #define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */
253 #define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */
254 #define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */
255 #define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
256 #define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
257 #define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */
260 #define TCV_PADDR_ETX 0 /* Internal transceiver */
264 #define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */
265 #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
282 #define DP83840_CSCONFIG 0x17 /* CS configuration */
285 #define CSCONFIG_RESV1 0x0001 /* Unused... */
286 #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
287 #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
288 #define CSCONFIG_RESV2 0x0008 /* Unused... */
289 #define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */
290 #define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */
291 #define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */
292 #define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */
293 #define CSCONFIG_RESV3 0x0700 /* Unused... */
294 #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
295 #define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */
296 #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
297 #define CSCONFIG_RESV4 0x4000 /* Unused... */
298 #define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */
313 #define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
314 #define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */
315 #define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */
316 #define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */
323 #define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
324 #define TXFLAG_SOP 0x40000000 /* 1 = start of packet */
325 #define TXFLAG_EOP 0x20000000 /* 1 = end of packet */
326 #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
327 #define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */
328 #define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */
329 #define TXFLAG_SIZE 0x00003fff /* Size of the packet */
334 #if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
381 ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
385 external = 0,
392 arbwait = 0, /* Waiting for auto negotiation to complete. */
465 #define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */
466 #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
467 #define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */
468 #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
469 #define HFLAG_FULL 0x00000020 /* Full duplex enable */
470 #define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */
471 #define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */
472 #define HFLAG_INIT 0x00000200 /* Init called at least once */
473 #define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */
474 #define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */
475 #define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */