Lines Matching +full:mac +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
54 #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
146 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
171 * them later. -DaveM
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
224 #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
225 #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
226 #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
227 #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
228 #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
233 #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
234 #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
235 #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
236 #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
237 #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
238 #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
257 * This 13-bit register is written by the host CPU and holds the last
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
297 * them later. -DaveM
300 /* MAC Registers */
301 #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/
302 #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/
304 #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
305 #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
306 #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */
307 #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
308 #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
309 #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */
310 #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
311 #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
312 #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */
323 #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */
324 #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
325 #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
326 #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
327 #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
328 #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
329 #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
330 #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
331 #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
332 #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
368 /* TX MAC Software Reset Command. */
369 #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
371 /* RX MAC Software Reset Command. */
372 #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
376 * Send_Pause and flow-control
379 #define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC
384 /* TX MAC Status Register. */
395 /* RX MAC Status Register. */
404 /* MAC Control Status Register. */
414 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
417 /* TX MAC Configuration Register.
419 * NOTE: The TX MAC Enable bit must be cleared and polled until
425 * mode must be enabled when in half-duplex at 1Gbps, else
428 #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
439 /* RX MAC Configuration Register.
441 * NOTE: The RX MAC Enable bit must be cleared and polled until
448 #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
451 #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
458 /* MAC Control Config Register. */
461 #define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */
465 * NOTE: When leaving or entering loopback mode, a global hardware
476 /* InterPacketGap0 Register. This 8-bit value is used as an extension
478 * timing of the RX-to-TX IPG. This value is ignored and presumed to
479 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
480 * is cleared in the TX MAC Configuration Register.
487 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
495 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
503 /* Slot Time Register. This 10-bit value specifies the slot time
510 /* Minimum Frame Size Register. This 10-bit register specifies the
522 * packets sent in half-duplex gigabit modes.
529 /* PA Size Register. This 10-bit register specifies the number of preamble
536 /* Jam Size Register. This 4-bit register specifies the duration of
542 /* Attempts Limit Register. This 8-bit register specifies the number
552 /* MAX Control Type Register. This 16-bit register specifies the
553 * "type" field of a MAC Control frame. The TXMAC uses this field to
554 * encapsulate the MAC Control frame for transmission, and the RXMAC
555 * uses it for decoding valid MAC Control frames received from the
561 /* MAC Address Registers. Each of these registers specify the
562 * ethernet MAC of the interface, 16-bits at a time. Register
567 * MAC address for the interface.
569 * Registers 6 through and including 8 specify the MAC Control
570 * Address, which must be the reserved multicast address for MAC
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
592 /* Statistics Registers. All of these registers are 16-bits and
599 /* Random Number Seed Register. This 10-bit value is used as the
602 * interfaces MAC address.
605 /* Pause Timer, read-only. This 16-bit timer is used to time the pause
607 * A non-zero value in this timer indicates that the MAC is currently in
612 #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
613 #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
614 #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
621 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
623 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
630 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
632 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
637 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
638 * ('1') or disable ('0') the I-directional driver on the MII when the
639 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
647 /* MIF Configuration Register. This 15-bit register controls the operation
652 #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
654 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
655 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
658 /* MIF Frame/Output Register. This 32-bit register allows the host to
659 * communicate with a transceiver in frame mode (as opposed to big-bang
660 * mode). Writes by the host specify an instrution. After being issued
674 * operating in the poll mode. The poll status field is auto-clearing
680 /* MIF Mask Register. This 16-bit register is used when in poll mode
693 #define PCS_DMODE 0x9050UL /* Datapath Mode Register */
701 #define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */
702 #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
705 #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
707 #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
716 #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
718 #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
727 #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
728 #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
741 #define PCS_CFG_JS 0x00000018 /* Jitter-study:
743 * 1 = high-frequency test pattern
744 * 2 = low-frequency test pattern
747 #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
749 /* PCS Interrupt Status Register. This register is self-clearing
754 /* Datapath Mode Register. */
756 #define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */
757 #define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */
762 * NOTE: When in SERDES mode, the loopback bit has inverse logic.
769 #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
806 /* MII BCM5400 1000-BASET Control register */
823 * control word. The same functionality is obtained via the TX-Kick
824 * and TX-Complete registers. As a result, GEM need not write back
871 #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
876 #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
880 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
930 #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
931 #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
934 (((GP)->tx_old <= (GP)->tx_new) ? \
935 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
936 (GP)->tx_old - (GP)->tx_new - 1)
939 #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
971 link_force_ret, /* Forced mode worked, retrying autoneg */
972 link_force_ok, /* Stay in forced mode */
981 unsigned int has_wol : 1; /* chip supports wake-on-lan */
1025 #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
1026 gp->phy_mii.def && gp->phy_mii.def->ops)