91 #define nr64(reg)		readq(np->regs + (reg))  macro
198 		u64 val = nr64(reg);  in __niu_wait_bits_clear()
225 			   (unsigned long long)nr64(reg));  in __niu_set_and_wait_clear()
260 	val = nr64(mask_reg);  in niu_ldn_irq_enable()
322 		val = nr64(MIF_FRAME_OUTPUT);  in mdio_wait()
527 		sig = nr64(ESR_INT_SIGNALS);  in serdes_init_niu_1g_serdes()
633 		sig = nr64(ESR_INT_SIGNALS);  in serdes_init_niu_10g_serdes()
857 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_10g()
903 	val = nr64(ENET_SERDES_1_PLL_CFG);  in serdes_init_1g()
981 	val_rd = nr64(ENET_SERDES_RESET);  in serdes_init_1g_serdes()
1022 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_1g_serdes()
1568 	val = nr64(MIF_CONFIG);  in xcvr_init_10g_bcm8706()
1625 	val = nr64(MIF_CONFIG);  in xcvr_init_10g()
1678 	val = nr64(MIF_CONFIG);  in xcvr_init_1g_rgmii()
1872 	val = nr64(MIF_CONFIG);  in xcvr_init_1g()
2127 	sig = nr64(ESR_INT_SIGNALS);  in niu_10g_phy_present()
2454 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_10g_serdes()
2769 	u64 reg_val = nr64(ENET_VLAN_TBL(index));  in vlan_tbl_write()
2797 		if (nr64(TCAM_CTL) & bit)  in tcam_wait_bit()
2825 		key[0] = nr64(TCAM_KEY_0);
2826 		key[1] = nr64(TCAM_KEY_1);
2827 		key[2] = nr64(TCAM_KEY_2);
2828 		key[3] = nr64(TCAM_KEY_3);
2829 		mask[0] = nr64(TCAM_KEY_MASK_0);
2830 		mask[1] = nr64(TCAM_KEY_MASK_1);
2831 		mask[2] = nr64(TCAM_KEY_MASK_2);
2832 		mask[3] = nr64(TCAM_KEY_MASK_3);
2862 		*data = nr64(TCAM_KEY_1);
2878 	u64 val = nr64(FFLP_CFG_1);  in tcam_enable()
2889 	u64 val = nr64(FFLP_CFG_1);  in tcam_set_lat_and_ratio()
2898 	val = nr64(FFLP_CFG_1);  in tcam_set_lat_and_ratio()
2914 	val = nr64(reg);  in tcam_user_eth_class_enable()
2937 	val = nr64(reg);
2957 	val = nr64(reg);  in tcam_user_ip_class_enable()
2982 	val = nr64(reg);  in tcam_user_ip_class_set()
3049 		data[i] = nr64(HASH_TBL_DATA(partition));
3087 	u64 val = nr64(FFLP_CFG_1);  in fflp_set_timings()
3093 	val = nr64(FFLP_CFG_1);  in fflp_set_timings()
3097 	val = nr64(FCRAM_REF_TMR);  in fflp_set_timings()
3117 	val = nr64(reg);  in fflp_set_partition()
3142 	u64 val = nr64(FFLP_CFG_1);  in fflp_llcsnap_enable()
3153 	u64 val = nr64(FFLP_CFG_1);  in fflp_errors_enable()
3668 	misc = nr64(RXMISC(rx_channel));  in niu_sync_rx_discard_stats()
3683 	wred = nr64(RED_DIS_CNT(rx_channel));  in niu_sync_rx_discard_stats()
3705 	stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));  in niu_rx_work()
3706 	qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;  in niu_rx_work()
3835 	u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));  in niu_rx_error()
3886 	cs = nr64(TX_CS(rp->tx_channel));  in niu_tx_error()
3887 	logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));  in niu_tx_error()
3888 	logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));  in niu_tx_error()
3903 	u64 mif_status = nr64(MIF_STATUS);  in niu_mif_interrupt()
4067 	u64 stat = nr64(SYS_ERR_STAT);  in niu_device_error()
4159 	rp->tx_cs = nr64(TX_CS(rp->tx_channel));  in niu_txchan_intr()
4225 	v0 = nr64(LDSV0(ldg));  in niu_interrupt()
4226 	v1 = nr64(LDSV1(ldg));  in niu_interrupt()
4227 	v2 = nr64(LDSV2(ldg));  in niu_interrupt()
4563 		u64 val = nr64(TX_CS(channel));  in niu_tx_cs_sng_poll()
4572 	u64 val = nr64(TX_CS(channel));  in niu_tx_channel_stop()
4585 		u64 val = nr64(TX_CS(channel));  in niu_tx_cs_reset_poll()
4594 	u64 val = nr64(TX_CS(channel));  in niu_tx_channel_reset()
4634 	val = nr64(TXC_CONTROL);  in niu_txc_enable_port()
4653 	val = nr64(TXC_INT_MASK);  in niu_txc_set_imask()
4905 	u64 val = nr64(RXDMA_CFIG1(channel));  in niu_enable_rx_channel()
4916 		if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)  in niu_enable_rx_channel()
4971 	val = nr64(RX_DMA_CTL_STAT(channel));  in niu_init_one_rx_channel()
5113 			   (unsigned long long)nr64(ZCP_RAM_ACC));  in niu_zcp_read()
5126 			   (unsigned long long)nr64(ZCP_RAM_ACC));  in niu_zcp_read()
5130 	data[0] = nr64(ZCP_RAM_DATA0);  in niu_zcp_read()
5131 	data[1] = nr64(ZCP_RAM_DATA1);  in niu_zcp_read()
5132 	data[2] = nr64(ZCP_RAM_DATA2);  in niu_zcp_read()
5133 	data[3] = nr64(ZCP_RAM_DATA3);  in niu_zcp_read()
5134 	data[4] = nr64(ZCP_RAM_DATA4);  in niu_zcp_read()
5141 	u64 val = nr64(RESET_CFIFO);  in niu_zcp_cfifo_reset()
5182 	(void) nr64(ZCP_INT_STAT);  in niu_init_zcp()
5294 		val = nr64(MIF_CONFIG);  in niu_init_xif_xmac()
6899 		val = nr64(ESPC_NCR((offset - b_offset) / 4));  in niu_get_eeprom()
6906 		val = nr64(ESPC_NCR(offset / 4));  in niu_get_eeprom()
6913 		val = nr64(ESPC_NCR(offset / 4));  in niu_get_eeprom()
7929 		if (nr64(LDG_NUM(ldn)) != ldg) {  in niu_ldg_assign_ldn()
7932 				(unsigned long long) nr64(LDG_NUM(ldn)));  in niu_ldg_assign_ldn()
7978 		frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
7993 		frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
8003 	frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
8384 	val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);  in niu_pci_probe_sprom()
8395 		val = nr64(ESPC_NCR(i));  in niu_pci_probe_sprom()
8408 	val = nr64(ESPC_PHY_TYPE);  in niu_pci_probe_sprom()
8468 	val = nr64(ESPC_MAC_ADDR0);  in niu_pci_probe_sprom()
8476 	val = nr64(ESPC_MAC_ADDR1);  in niu_pci_probe_sprom()
8495 	val = nr64(ESPC_MOD_STR_LEN);  in niu_pci_probe_sprom()
8502 		u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));  in niu_pci_probe_sprom()
8511 	val = nr64(ESPC_BD_MOD_STR_LEN);  in niu_pci_probe_sprom()
8518 		u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));  in niu_pci_probe_sprom()
8528 		nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;  in niu_pci_probe_sprom()
8551 				parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &  in niu_get_and_validate_port()