Lines Matching +full:rx +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
31 * shared between cassini and cassini+. REG_PLUS_ addresses only
32 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
87 #define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
91 RX complete head incr to
92 almost reach RX complete
104 len of non-reassembly pkt
118 #define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
149 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
205 * reset. poll until TX and RX read back as 0's for completion.
210 #define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
216 reset when hot-swap is being
253 /* Cassini only. 64-bit register used to check PCI datapath. when read,
254 * value written has both lower and upper 32-bit halves rotated to the right
255 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
277 #define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
286 #define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
293 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
294 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
300 Cassini only. reserved in
305 buffer. Cassini only. reserved
310 Cassini only. reserved in
313 Cassini only. reserved in
338 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
347 0x0C = rx[1:0]
361 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
363 * all of the alternate (2-4) INTR registers while _1 corresponds to only
380 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
386 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
390 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
420 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
440 #define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
457 #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
474 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
475 * used for diagnostics only.
480 diagnostics only. */
485 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
504 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
521 /* values of TX_COMPLETE_1-4 are written. each completion register
523 * NOTE: completion reg values are only written back prior to TX_INTME and
524 * TX_ALL interrupts. at all other times, the most up-to-date index values
549 * be 2KB-aligned. */
555 /* 16-bit registers hold weights for the weighted round-robin of the
560 * these registers causes a queue1 pre-emption with all historical bw
562 * pre-emption/re-allocation of network bandwidth
583 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
602 * free ring size = (1 << n)*32 -> [32 - 8k]
603 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
606 #define REG_RX_CFG 0x4000 /* RX config */
607 #define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
612 RX */
613 #define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
617 #define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
634 /* cassini+ only */
636 RX free desc ring 2.
643 * [--------------------------------------------------------------] page
645 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
653 #define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
684 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
686 * DEFAULT: 0x0. generated on 64-bit boundaries.
688 #define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
689 #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
690 #define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
692 #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
694 #define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
695 pointer. (8-bit counter) */
697 /* current state of RX DMA state engines + other info
700 #define REG_RX_DEBUG 0x401C /* RX debug */
712 RX FIFO:
762 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
766 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
770 #define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
773 RX FIFO occupancy >
777 emitting XOFF PAUSE when RX
785 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
786 * valid RX descriptors are available, Cassini will read 4 at a time.
788 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
791 #define REG_RX_KICK 0x4024 /* RX kick reg */
793 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
794 * lower 13 bits of the low register are hard-wired to 0.
796 #define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
798 #define REG_RX_DB_HI 0x402C /* RX descriptor ring
800 #define REG_RX_CB_LOW 0x4030 /* RX completion ring
802 #define REG_RX_CB_HI 0x4034 /* RX completion ring
804 /* 13-bit register indicate desc used by cassini for receive frames. used
808 #define REG_RX_COMP 0x4038 /* (ro) RX completion */
810 /* HEAD and TAIL are used to control RX desc posting and interrupt
820 #define REG_RX_COMP_HEAD 0x403C /* RX completion head */
821 #define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
826 #define REG_RX_BLANK 0x4044 /* RX blanking register
848 #define REG_RX_AE_THRESH 0x4048 /* RX almost empty
868 #define REG_RX_RED 0x404C /* RX random early detect enable */
874 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
875 * RX control FIFO = # of packets in RX FIFO.
878 #define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
881 #define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
882 #define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
883 #define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
884 #define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
887 /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
892 #define REG_RX_BIST 0x4060 /* (ro) RX BIST */
893 #define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */
894 #define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */
895 #define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */
896 #define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */
897 #define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */
898 #define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */
899 #define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */
900 #define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */
901 #define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */
902 #define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */
903 #define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */
904 #define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */
905 #define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */
906 #define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */
907 #define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */
908 #define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */
909 #define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
920 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
924 #define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
926 #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
933 #define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
949 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
953 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
957 #define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
958 #define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
959 #define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */
960 #define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */
961 #define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */
963 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
964 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
965 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
966 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
970 #define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
972 #define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
974 #define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
976 #define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
981 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
984 #define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */
985 #define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */
986 #define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */
987 #define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high
989 #define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high
992 /* 64-bit pointer to receive data buffer in host memory used for headers and
994 * increments as DMA writes receive data. only 50 LSB are incremented. top
995 * 13 bits taken from RX descriptor.
998 #define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr
1000 #define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
1002 #define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
1004 #define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
1007 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1008 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1016 #define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table
1020 #define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
1022 #define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
1024 #define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
1027 /* cassini+ only */
1028 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1031 #define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring
1033 #define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring
1035 #define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring
1037 #define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring
1039 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1040 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1041 #define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
1042 #define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
1044 #define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
1046 #define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
1048 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1049 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1050 #define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2
1057 /* RX parser configuration register.
1074 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1076 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1082 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1116 /* PIO access into RX Header parser data RAM and flow database.
1117 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1119 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1120 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1122 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1132 #define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1136 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1148 /* diagnostics for RX Header Parser block.
1226 /* reset bits are set using a PIO write and self-cleared after the command
1231 #define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset
1243 /* bit set indicates that event occurred. auto-cleared when status register
1272 #define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
1276 RX FIFO overflow */
1310 /* layout identical to RX MAC[6:0] */
1311 #define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
1319 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1321 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1342 Rx-to-TX IPG. after
1352 back-to-pack (Tx-to-Tx
1354 IPG0 and will only use
1388 will only commit to frame
1408 for half-duplex at 1Gbps,
1413 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1415 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1420 #define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
1421 #define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
1424 #define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
1433 #define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
1439 RX DMA by setting BAD
1452 senders. only applies
1453 to half-duplex 1Gbps */
1463 packets to RX DMA */
1467 * a hw or global sw reset, RX/TX MAC software reset and initialization
1489 or in half-duplex SERDES
1491 in half-duplex when
1502 #define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
1504 #define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
1506 #define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
1549 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1554 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1580 mask reg. 8-bit reg
1586 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1587 * 16-bit registers contain bits of the hash table.
1588 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1589 * e.g., 15 -> [15:0], 0 -> [255:240]
1595 * overflow. recommended initialization: 0x0000. most are 16-bits except
1614 #define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation
1619 10-bit register used as a
1622 backoff algorithm. only
1623 programmed after power-on
1636 /* 27-bit register has the current state for key state machines in the MAC */
1655 /** MIF registers. the MIF can be programmed in either bit-bang or
1658 #define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1659 1 -> 0 will generate a
1660 rising edge. 0 -> 1 will
1662 #define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1664 #define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1669 /* 32-bit register serves as an instruction register when the MIF is
1673 * contain the 16-bit data returned by the tranceiver. unless specified
1709 load with 16-bit data
1717 and 16-bit data
1723 #define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
1724 0 -> select MDIO_0 */
1728 #define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
1729 0 -> frame mode */
1732 only meaningful if POLL_EN
1737 1 -> tranceiver is
1740 w/ MDIO_0 in bit-bang
1746 1 -> transceiver is
1749 w/ MDIO_1 in bit-bang
1757 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1764 /* 32-bit register used when in poll mode. auto-cleared after being read */
1779 /* 7-bit register has current state for all state machines in the MIF */
1791 /* the auto-negotiation enable bit should be programmed the same at
1792 * the link partner as in the local device to enable auto-negotiation to
1793 * complete. when that bit is reprogrammed, auto-neg/manual config is
1808 restart auto-
1823 #define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1830 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1831 0 -> link down. 0 is
1837 auto-neg) */
1838 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
1840 word. only valid after
1841 auto-neg completed */
1842 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1844 0 -> auto-negotiation not
1848 a 1000 Base-X PHY. writes
1851 /* used during auto-negotiation.
1857 1000 Base-X */
1858 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
1859 1000 Base-X */
1867 going off-line. bit12 will
1895 non-resettable */
1910 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1915 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1927 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
1930 through 0-1 indicates
1968 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1986 10-bit interface */
1996 #define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2006 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2009 * 0b101 R period RX, R period TX, R period HP, R period BIM
2037 /** LocalBus Devices. the following provides run-time access to the
2091 #define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2515 * RX DESC and COMP rings must be 8KB aligned
2525 #define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */
2544 /* number of flows that can go through re-assembly */
2570 bytes. 0 - 9256 */
2589 #define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only.
2598 /* descriptor ring for free buffers contains page-sized buffers. the index
2671 /* we encode the following: ring/index/release. only 14 bits
2706 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2707 * TX COMPWB must be 8-byte aligned.
2743 spinlock_t rx_inuse_lock; /* rx inuse list */
2744 spinlock_t rx_spare_lock; /* rx spare list */
2765 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2766 * are there for flow re-assembly. */
2805 int crc_size; /* 4 if half-duplex */
2833 /* Link-down problem workaround */
2850 int casreg_len; /* reg-space size for dumping */
2867 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2868 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2869 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2871 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2872 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2874 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2875 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2876 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2879 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))