Lines Matching +full:0 +full:x4120
8 * vendor id: 0x108E (Sun Microsystems, Inc.)
9 * device id: 0xabba (Cassini)
10 * revision ids: 0x01 = Cassini
11 * 0x02 = Cassini rev 2
12 * 0x10 = Cassini+
13 * 0x11 = Cassini+ 0.2u
15 * vendor id: 0x100b (National Semiconductor)
16 * device id: 0x0035 (DP83065/Saturn)
17 * revision ids: 0x30 = Saturn B2
19 * rings are all offset from 0.
34 #define CAS_ID_REV2 0x02
35 #define CAS_ID_REVPLUS 0x10
36 #define CAS_ID_REVPLUS02u 0x11
37 #define CAS_ID_REVSATURNB2 0x30
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
44 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
45 * DEFAULT: 0x0, SIZE: 5 bits
47 #define REG_CAWR 0x0004 /* core arbitration weight */
48 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
49 #define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */
51 #define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */
52 #define CAWR_RR_DIS 0x10 /* [4] */
57 * DEFAULT: 0x0, SIZE: 1 bit
59 #define REG_INF_BURST 0x0008 /* infinite burst enable reg */
60 #define INF_BURST_EN 0x1 /* enable */
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
65 * DEFAULT: 0x00000000, SIZE: 29 bits
67 #define REG_INTR_STATUS 0x000C /* interrupt status register */
68 #define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
71 #define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
76 #define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
78 #define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
80 #define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
85 #define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
87 #define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
89 #define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
94 #define INTR_RX_BUF_AE 0x00000100 /* less than the
98 #define INTR_RX_COMP_AF 0x00000200 /* less than the
103 #define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC !=
110 #define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
115 #define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
116 #define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
118 #define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
120 #define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
123 #define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
125 #define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
128 #define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
139 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
141 #define REG_INTR_MASK 0x0010 /* Interrupt mask */
145 * DEFAULT: 0x00000000, SIZE: 12 bits
147 #define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
151 * DEFAULT: 0x00000000, SIZE: 29 bits
153 #define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
156 /* DEFAULT: 0x0, SIZE: 3 bits */
157 #define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
158 #define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
161 #define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
163 #define PCI_ERR_OTHER 0x04 /* other PCI errors */
164 #define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req.
166 #define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
168 #define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
173 * DEFAULT: 0x7, SIZE: 3 bits
175 #define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
178 * DEFAULT: 0bxx000, SIZE: 5 bits
180 #define REG_BIM_CFG 0x1008 /* BIM Configuration */
181 #define BIM_CFG_RESERVED0 0x001 /* reserved */
182 #define BIM_CFG_RESERVED1 0x002 /* reserved */
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
184 #define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
186 #define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */
187 #define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
188 #define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
189 #define BIM_CFG_RESERVED2 0x100 /* reserved */
190 #define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
192 #define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
194 #define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0.
197 /* DEFAULT: 0x00000000, SIZE: 32 bits */
198 #define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
199 #define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
200 machine bits [21:0] */
201 #define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
202 machine bits [6:0] */
205 * reset. poll until TX and RX read back as 0's for completion.
207 #define REG_SW_RESET 0x1010 /* Software reset */
208 #define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until
209 cleared to 0. */
210 #define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
211 cleared to 0. */
212 #define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
218 #define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
222 #define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
223 #define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
224 0b000: ARB_IDLE1
225 0b001: ARB_IDLE2
226 0b010: ARB_WB_ACK
227 0b011: ARB_WB_WAT
228 0b100: ARB_RB_ACK
229 0b101: ARB_RB_WAT
230 0b110: ARB_RB_END
231 0b111: ARB_WB_END */
232 #define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
233 0b00: RD_PCI_WAT
234 0b01: RD_PCI_RDY
235 0b11: RD_PCI_ACK */
236 #define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
237 0b00: AD_IDL_RX
238 0b01: AD_ACK_RX
239 0b10: AD_ACK_TX
240 0b11: AD_IDL_TX */
241 #define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
242 0b00: WR_PCI_WAT
243 0b01: WR_PCI_RDY
244 0b11: WR_PCI_ACK */
245 #define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits:
246 0b000: ARB_IDLE1
247 0b001: ARB_IDLE2
248 0b010: ARB_TX_ACK
249 0b011: ARB_TX_WAT
250 0b100: ARB_RX_ACK
251 0b110: ARB_RX_WAT */
257 #define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
263 * DEFAULT: 0x7
265 #define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
266 output EN. default: 0x7 */
267 #define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
271 bus devices. tristate when 0. */
272 #define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
273 #define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
275 #define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */
276 #define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */
277 #define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
284 #define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
286 #define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
287 #define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1
288 read buffer access = 0 */
290 #define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
291 #define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
296 #define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
298 #define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
299 #define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
302 #define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
304 #define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write
307 #define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
308 #define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
309 #define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
312 #define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
317 * DEFAULT: 0xFC
319 #define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
324 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
326 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
329 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
331 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
333 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
334 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
335 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
336 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
338 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
339 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
341 #define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
342 #define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
343 driven on local bus P_A[15:0]
345 #define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
346 0x03 = mac[1:0]
347 0x0C = rx[1:0]
348 0x30 = tx[1:0]
349 0xC0 = hp[1:0] */
350 #define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
353 #define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
354 on P_A[7:0]. see above for
358 DEFAULT: 0x1F */
359 #define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
365 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
367 #define INTR_RX_DONE_ALT 0x01
368 #define INTR_RX_COMP_FULL_ALT 0x02
369 #define INTR_RX_COMP_AF_ALT 0x04
370 #define INTR_RX_BUF_UNAVAIL_1 0x08
371 #define INTR_RX_BUF_AE_1 0x10 /* almost empty */
372 #define INTRN_MASK_RX_EN 0x80
378 #define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status
379 register 2 for INTB. default: 0x1F */
381 #define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the
384 #define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
388 #define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
392 #define REG_SATURN_PCFG 0x106c /* pin configuration register for
395 #define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */
396 #define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */
397 #define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
398 #define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
399 #define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
400 #define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
401 0 = normal */
402 #define SATURN_PCFG_MTP 0x00000080 /* test point select */
403 #define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
406 #define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
410 #define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
423 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
424 * DEFAULT: 0x3F000001
426 #define REG_TX_CFG 0x2004 /* TX config */
427 #define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
430 #define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
435 #define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
440 #define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
442 if 0, TX_ALL set
444 #define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
445 #define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at
448 #define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at
451 #define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at
454 #define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at
457 #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
459 #define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
461 0b00: tx mac req,
464 0b01: txdma rd req,
468 0b11: txdma wr req,
477 #define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
478 #define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
481 #define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
482 #define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
486 #define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */
489 #define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */
490 #define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */
491 #define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */
492 #define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine.
493 = 0x01 when TX disabled. */
494 #define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */
495 #define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
497 #define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
499 #define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
500 #define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
501 #define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
502 #define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */
507 #define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
508 #define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
514 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
516 #define REG_TX_KICK0 0x2038 /* TX kick reg #1 */
518 #define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
528 * 0 TX_COMPLETE_1_MSB
538 #define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back
540 #define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back
542 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
543 #define TX_COMPWB_MSB_SHIFT 0
544 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
548 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
550 #define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
551 #define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */
561 * deficit data reset to 0 (useful when congestion requires a
564 #define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */
565 #define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */
566 #define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */
567 #define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */
576 #define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
577 #define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
578 #define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */
579 #define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */
580 #define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
581 #define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
586 #define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
587 #define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
589 #define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
590 #define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
591 #define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */
592 #define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */
593 #define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */
594 #define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self
601 /* receive DMA channel configuration. default: 0x80910
604 * DEFAULT: 0x80910
606 #define REG_RX_CFG 0x4000 /* RX config */
607 #define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
613 #define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
615 def: 0x8 = 8k */
617 #define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
618 ring. def: 0x8 = 32k */
620 #define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
621 batching. def: 0x0 =
623 #define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
631 buffers. def: 0x2 */
635 #define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
637 def: 0x8 = 8k */
651 * DEFAULT: 0x48002002 (8k pages)
653 #define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
654 #define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
659 0b00 = 2k, 0b01 = 4k
660 0b10 = 8k, 0b11 = 16k
662 #define RX_PAGE_SIZE_SHIFT 0
663 #define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
667 #define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
671 0b00 = 1k, 0b01 = 2k
672 0b10 = 4k, 0b11 = 8k
673 DEFAULT: 0x1 */
675 #define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
678 0b00 = 0,
679 0b01 = 64 bytes
680 0b10 = 96, 0b11 = 128
681 DEFAULT: 0x1 */
686 * DEFAULT: 0x0. generated on 64-bit boundaries.
688 #define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
689 #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
690 #define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
692 #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
694 #define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
698 * DEFAULT: 0x0
700 #define REG_RX_DEBUG 0x401C /* RX debug */
701 #define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC:
702 0x0 = idle, 0x1 = load_bop
703 0x2 = load 1, 0x3 = load 2
704 0x4 = load 3, 0x5 = load 4
705 0x6 = last detect
706 0x7 = wait req
707 0x8 = wait req statuss 1st
708 0x9 = load st
709 0xa = bubble mac
710 0xb = error */
711 #define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and
713 0x0 = idle, 0x1 = hp xfr
714 0x2 = wait hp ready
715 0x3 = wait flow code
716 0x4 = fifo xfer
717 0x5 = make status
718 0x6 = csum ready
719 0x7 = error */
720 #define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine
722 0x0 = idle
723 0x1 = wait xoff ack
724 0x2 = wait xon
725 0x3 = wait xon ack */
726 #define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
728 0x0 = idle data
729 0x1 = header begin
730 0x2 = xfer header
731 0x3 = xfer header ld
732 0x4 = mtu begin
733 0x5 = xfer mtu
734 0x6 = xfer mtu ld
735 0x7 = jumbo begin
736 0x8 = xfer jumbo
737 0x9 = xfer jumbo ld
738 0xa = reas begin
739 0xb = xfer reas
740 0xc = flush tag
741 0xd = xfer reas ld
742 0xe = error
743 0xf = bubble idle */
744 #define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine
746 0x0 = idle desc
747 0x1 = wait ack
748 0x9 = wait ack 2
749 0x2 = fetch desc 1
750 0xa = fetch desc 2
751 0x3 = load ptrs
752 0x4 = wait dma
753 0x5 = wait ack batch
754 0x6 = post batch
755 0x7 = xfr done */
756 #define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
758 #define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer
763 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
766 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
767 * value is 0x6F.
768 * DEFAULT: 0x00078
770 #define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
772 #define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
775 #define RX_PAUSE_THRESH_OFF_SHIFT 0
776 #define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
788 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
789 * DEFAULT: 0 on reset
791 #define REG_RX_KICK 0x4024 /* RX kick reg */
794 * lower 13 bits of the low register are hard-wired to 0.
796 #define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
798 #define REG_RX_DB_HI 0x402C /* RX descriptor ring
800 #define REG_RX_CB_LOW 0x4030 /* RX completion ring
802 #define REG_RX_CB_HI 0x4034 /* RX completion ring
806 * DEFAULT: 0 on reset
808 #define REG_RX_COMP 0x4038 /* (ro) RX completion */
818 * DEFAULT: 0 on reset
820 #define REG_RX_COMP_HEAD 0x403C /* RX completion head */
821 #define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
824 * DEFAULT: 0x00000000
826 #define REG_RX_BLANK 0x4044 /* RX blanking register
828 #define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
832 the ISR was read. 0 = no
834 #define RX_BLANK_INTR_PKT_SHIFT 0
835 #define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted
840 clocks (125MHz). 0 = no
846 * DEFAULT: 0x00000000
848 #define REG_RX_AE_THRESH 0x4048 /* RX almost empty
850 #define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be
854 #define RX_AE_THRESH_FREE_SHIFT 0
855 #define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be
865 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
866 * DEFAULT: 0x00000000
868 #define REG_RX_RED 0x404C /* RX random early detect enable */
869 #define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */
870 #define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */
871 #define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */
872 #define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */
876 * DEFAULT: 0x0
878 #define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
879 #define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */
880 #define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */
881 #define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
882 #define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
883 #define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
884 #define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
890 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
892 #define REG_RX_BIST 0x4060 /* (ro) RX BIST */
893 #define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */
894 #define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */
895 #define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */
896 #define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */
897 #define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */
898 #define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */
899 #define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */
900 #define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */
901 #define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */
902 #define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */
903 #define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */
904 #define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */
905 #define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */
906 #define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */
907 #define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */
908 #define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */
909 #define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
910 #define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */
911 #define RX_BIST_SUMMARY 0x00000002 /* when BIST complete,
916 #define RX_BIST_START 0x00000001 /* write 1 to start
922 * DEFAULT: 0
924 #define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
926 #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
931 * DEFAULT: 0x0
933 #define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
935 #define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if #
938 read. 0 = no
942 #define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if #
946 (125MHz). 0 = no
952 * to normal operation after diagnostics, write to address location 0x0.
953 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
957 #define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
958 #define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
959 #define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */
960 #define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */
961 #define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */
966 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
970 #define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
972 #define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
974 #define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
976 #define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
978 #define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */
979 #define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */
984 #define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */
985 #define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */
986 #define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */
987 #define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high
989 #define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high
998 #define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr
1000 #define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
1002 #define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
1004 #define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
1011 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1013 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1016 #define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table
1018 #define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */
1020 #define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
1022 #define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
1024 #define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
1029 * 0. same semantics as primary desc/complete rings.
1031 #define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring
1033 #define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring
1035 #define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring
1037 #define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring
1041 #define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
1042 #define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
1044 #define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
1046 #define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
1050 #define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2
1058 * DEFAULT: 0x1651004
1060 #define REG_HP_CFG 0x4140 /* header parser
1062 #define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */
1063 #define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors
1064 0 = 64. 0x3f = 63 */
1066 #define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment
1069 #define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data
1076 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1080 #define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM
1082 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1083 #define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM
1085 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1086 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1087 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1089 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1091 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1093 #define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM
1095 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1096 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1097 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1099 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1101 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1103 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1105 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1107 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1109 #define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM
1111 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1112 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1113 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1119 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1122 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1126 #define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB
1128 #define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte
1132 #define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1134 #define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */
1136 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1138 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1140 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1141 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1142 * FLOW_DB(10) = bit 0 has value for flow valid
1143 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1145 #define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */
1152 #define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */
1153 #define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */
1154 #define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */
1155 #define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
1156 #define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU
1158 #define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */
1160 #define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */
1161 #define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */
1162 #define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */
1163 #define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */
1164 #define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */
1166 #define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */
1167 #define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
1168 #define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start
1170 #define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */
1171 #define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */
1172 #define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o
1174 #define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split
1176 #define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload
1178 #define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
1180 #define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload
1182 #define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
1184 #define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
1185 #define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */
1186 #define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */
1187 #define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */
1188 #define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */
1189 #define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */
1196 #define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */
1197 #define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */
1198 #define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */
1199 #define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */
1200 #define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */
1201 #define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */
1202 #define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */
1203 #define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0
1204 bank 0 */
1205 #define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1
1206 bank 0 */
1207 #define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2
1208 bank 0 */
1209 #define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3
1210 bank 0 */
1211 #define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0
1213 #define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1
1215 #define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2
1217 #define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3
1219 #define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence
1221 #define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */
1222 #define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */
1229 #define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset
1230 command (default: 0x0) */
1231 #define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset
1232 command (default: 0x0) */
1234 DEFAULT: 0x0XXXX */
1235 #define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */
1236 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time
1240 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl
1245 * trigger an interrupt if the corresponding mask bit is 0.
1246 * status register default: 0x00000000
1247 * mask register default = 0xFFFFFFFF on reset
1249 #define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
1250 #define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
1252 #define MAC_TX_UNDERRUN 0x0002 /* terminated frame
1256 #define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed
1259 #define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal
1261 #define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive
1263 #define MAC_TX_COLL_LATE 0x0020 /* rollover of the late
1265 #define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first
1267 #define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer
1269 #define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak
1272 #define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
1273 #define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of
1275 #define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to
1277 #define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
1279 #define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment
1281 #define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
1283 #define MAC_RX_LEN_ERR 0x0020 /* rollover of length
1285 #define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
1288 /* DEFAULT: 0xXXXX0000 on reset */
1289 #define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */
1290 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful
1294 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a
1298 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a
1302 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time
1308 /* layout identical to TX MAC[8:0] */
1309 #define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */
1310 /* layout identical to RX MAC[6:0] */
1311 #define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
1312 /* layout identical to CTRL MAC[2:0] */
1313 #define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
1315 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1320 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1323 * be 0x200 (slot time of 512 bytes)
1325 #define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */
1326 #define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will
1333 #define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral
1335 full duplex and 0 when
1337 #define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff
1339 full duplex and 0 when
1341 #define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the
1351 0 or when xmitting frames
1357 #define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily
1366 GIVE_UP_LIM. when 0,
1369 #define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will
1372 0, TX MAC will continue
1377 #define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable
1383 #define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that
1392 #define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate
1399 #define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the
1417 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1420 #define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
1421 #define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
1422 #define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0.
1424 #define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
1427 #define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */
1428 #define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid
1431 #define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter
1433 #define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
1438 #define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to
1448 #define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of
1455 /* DEFAULT: 0x0 */
1456 #define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */
1457 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for
1460 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received
1462 #define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl
1469 * DEFAULT: 0x0
1471 #define REG_MAC_XIF_CFG 0x603C /* XIF config reg */
1472 #define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers
1474 #define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data
1482 entire mac core. 0 for
1484 #define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data
1486 xmission. clear to 0
1493 #define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII
1495 #define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable
1499 #define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */
1500 #define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */
1502 #define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
1503 recommended: 0x00 */
1504 #define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
1505 recommended: 0x08 */
1506 #define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
1507 recommended: 0x04 */
1508 #define REG_MAC_SLOT_TIME 0x604C /* slot time reg
1509 recommended: 0x40 */
1510 #define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg
1511 recommended: 0x40 */
1514 * recommended value: 0x2000.05EE
1516 #define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */
1517 #define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */
1519 #define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */
1520 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1521 #define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of
1527 value: 0x07 */
1528 #define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration
1531 value: 0x04 */
1532 #define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. #
1543 value: 0x10 */
1544 #define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg.
1547 value: 0x8808 */
1549 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1551 * 0 16 MSB of primary MAC addr [47:32] of DA field
1553 * 2 16 LSB "" [15:0] of DA field
1556 * 5*x 16 LSB "" [15:0]
1559 * 44 16 LSB "" [15:0]
1566 * primary addr reg 2 reg 1 reg 0
1571 #define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */
1573 #define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg
1575 #define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg
1577 #define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg
1578 [15:0] */
1579 #define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1
1583 #define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
1586 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1589 * e.g., 15 -> [15:0], 0 -> [255:240]
1591 #define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */
1595 * overflow. recommended initialization: 0x0000. most are 16-bits except
1598 #define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision
1600 #define REG_MAC_COLL_FIRST 0x61A4 /* first attempt
1603 #define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision
1605 #define REG_MAC_COLL_LATE 0x61AC /* late collision counter */
1606 #define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base
1609 #define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */
1610 #define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */
1611 #define REG_MAC_LEN_ERR 0x61BC /* length error counter */
1612 #define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */
1613 #define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */
1614 #define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation
1618 #define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg.
1637 #define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */
1638 #define MAC_SM_RLM_MASK 0x07800000
1640 #define MAC_SM_RX_FC_MASK 0x00700000
1642 #define MAC_SM_TLM_MASK 0x000F0000
1644 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1646 #define MAC_SM_TX_REQ_MASK 0x00000C00
1648 #define MAC_SM_TX_FC_MASK 0x000003C0
1650 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1652 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1653 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1658 #define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1659 1 -> 0 will generate a
1660 rising edge. 0 -> 1 will
1662 #define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1664 #define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1677 #define REG_MIF_FRAME 0x620C /* MIF frame/output reg */
1678 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame.
1681 #define MIF_FRAME_ST 0x40000000 /* STart of frame */
1682 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a
1685 #define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
1686 #define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */
1687 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when
1693 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address.
1698 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB.
1701 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB.
1703 set this bit to 0.
1708 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload
1722 #define REG_MIF_CFG 0x6210 /* MIF config reg */
1723 #define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
1724 0 -> select MDIO_0 */
1725 #define MIF_CFG_POLL_EN 0x0002 /* enable polling
1727 BB_MODE should be 0 */
1728 #define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
1729 0 -> frame mode */
1730 #define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be
1735 #define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
1744 #define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose.
1753 #define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to
1758 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1760 * set. DEFAULT: 0xFFFF
1762 #define REG_MIF_MASK 0x6214 /* MIF mask reg */
1765 #define REG_MIF_STATUS 0x6218 /* MIF status reg */
1766 #define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains
1771 #define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates
1777 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1780 #define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */
1781 #define MIF_SM_CONTROL_MASK 0x07 /* control state machine
1783 #define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine
1795 * DEFAULT: 0x1040
1797 #define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */
1798 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on
1800 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS
1804 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS
1807 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing.
1810 #define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
1812 #define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored
1814 #define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes
1817 can be used. when 0,
1821 #define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
1823 #define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1826 /* DEFAULT: 0x0108 */
1827 #define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */
1828 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */
1829 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */
1830 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1831 0 -> link down. 0 is
1832 latched so that 0 is
1836 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform
1838 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
1842 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1844 0 -> auto-negotiation not
1846 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an
1852 * DEFAULT: 0x00E0
1854 #define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement
1856 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex
1858 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
1860 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE
1862 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE
1864 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13
1872 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */
1873 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */
1878 #define REG_PCS_MII_LPA 0x900C /* PCS MII link partner
1888 /* DEFAULT: 0x0 */
1889 #define REG_PCS_CFG 0x9010 /* PCS config reg */
1890 #define PCS_CFG_EN 0x01 /* enable PCS. must be
1891 0 when modifying
1893 #define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to
1896 #define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation
1900 #define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter
1904 0x0 = normal operation
1905 0x1 = high freq test
1907 0x2 = low freq test
1909 0x3 = reserved */
1910 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1916 #define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine
1918 #define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate
1922 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception
1925 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of
1927 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
1930 through 0-1 indicates
1932 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1933 #define SM_LINK_STATE_UP 0x00016000 /* link state is up */
1935 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to
1938 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to
1940 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes
1944 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to
1947 C codes w/ 0 content
1953 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being
1956 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or
1958 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not
1960 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes
1962 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues
1971 #define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */
1972 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed
1979 #define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */
1980 #define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and
1985 #define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the
1989 #define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */
1990 #define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on
1992 #define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier
1994 0x0 for normal
1996 #define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2003 * should be 0x0 for normal operations.
2004 * 0b000 normal operation, PROM address[3:0] selected
2005 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2006 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2007 * 0b011 txmac req, tx ack, tx tag, tx retry req
2008 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2009 * 0b101 R period RX, R period TX, R period HP, R period BIM
2010 * DEFAULT: 0x0
2012 #define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */
2013 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2017 * 0b00 undergoing reset
2018 * 0b01 waiting 500us while lockrefn is asserted
2019 * 0b10 waiting for comma detect
2020 * 0b11 receive data is synchronized
2021 * DEFAULT: 0x0
2023 #define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */
2024 #define PCS_SERDES_STATE_MASK 0x03
2028 * DEFAULT: 0x0
2030 #define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */
2031 #define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */
2032 #define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS
2040 #define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time
2042 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2044 #define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus
2046 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2050 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2051 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2052 #define ENTROPY_STATUS_DRDY 0x01
2053 #define ENTROPY_STATUS_BUSY 0x02
2054 #define ENTROPY_STATUS_CIPHER 0x04
2055 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2056 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2057 #define ENTROPY_MODE_KEY_MASK 0x07
2058 #define ENTROPY_MODE_ENCRYPT 0x40
2059 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2060 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2061 #define ENTROPY_RESET_DES_IO 0x01
2062 #define ENTROPY_RESET_STC_MODE 0x02
2063 #define ENTROPY_RESET_KEY_CACHE 0x04
2064 #define ENTROPY_RESET_IV 0x08
2065 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2066 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2070 #define PHY_LUCENT_B0 0x00437421
2071 #define LUCENT_MII_REG 0x1F
2073 #define PHY_NS_DP83065 0x20005c78
2074 #define DP83065_MII_MEM 0x16
2075 #define DP83065_MII_REGD 0x1D
2076 #define DP83065_MII_REGE 0x1E
2078 #define PHY_BROADCOM_5411 0x00206071
2079 #define PHY_BROADCOM_B0 0x00206050
2080 #define BROADCOM_MII_REG4 0x14
2081 #define BROADCOM_MII_REG5 0x15
2082 #define BROADCOM_MII_REG7 0x17
2083 #define BROADCOM_MII_REG8 0x18
2085 #define CAS_MII_ANNPTR 0x07
2086 #define CAS_MII_ANNPRR 0x08
2087 #define CAS_MII_1000_CTRL 0x09
2088 #define CAS_MII_1000_STATUS 0x0A
2089 #define CAS_MII_1000_EXTEND 0x0F
2091 #define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2098 #define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */
2100 #define CAS_ADVERTISE_1000HALF 0x0100
2101 #define CAS_ADVERTISE_1000FULL 0x0200
2102 #define CAS_ADVERTISE_PAUSE 0x0400
2103 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2110 #define CAS_LPA_1000HALF 0x0400
2111 #define CAS_LPA_1000FULL 0x0800
2113 #define CAS_EXTEND_1000XFULL 0x8000
2114 #define CAS_EXTEND_1000XHALF 0x4000
2115 #define CAS_EXTEND_1000TFULL 0x2000
2116 #define CAS_EXTEND_1000THALF 0x1000
2131 u8 outenab; /* output enable: 0 = not, 1 = if match
2138 #define OP_EQ 0 /* packet == value */
2144 #define CL_REG 0
2162 #define S1_PCKT 0
2190 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
2191 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2192 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
2193 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2194 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
2195 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2196 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
2197 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2198 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
2199 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2200 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2201 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2202 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
2203 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2204 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
2205 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2206 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
2207 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2208 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
2209 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
2210 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
2211 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2212 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
2213 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2214 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
2215 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
2216 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2217 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2223 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2224 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2225 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2226 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2227 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2228 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2229 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2230 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2231 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2232 IM_CTL, 0x001, 3, 0x0, 0x0001},
2233 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2234 IM_CTL, 0x000, 0, 0x0, 0x0000},
2235 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2236 IM_CTL, 0x080, 3, 0x0, 0xffff},
2252 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2253 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */
2254 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2255 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */
2256 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2257 LD_R1, 0x205, 3, 0xB, 0xf000},
2258 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2259 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2260 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2261 IM_CTL, 0x001, 3, 0x0, 0x0001},
2262 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2263 CL_REG, 0x002, 3, 0x0, 0x0000},
2264 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2265 IM_CTL, 0x080, 3, 0x0, 0xffff},
2266 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2267 IM_CTL, 0x044, 3, 0x0, 0xffff},
2288 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
2289 CL_REG, 0x3ff, 1, 0x0, 0x0000},
2290 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2291 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2292 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
2293 CL_REG, 0x000, 0, 0x0, 0x0000},
2294 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2295 CL_REG, 0x000, 0, 0x0, 0x0000},
2296 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
2297 CL_REG, 0x000, 0, 0x0, 0x0000},
2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2299 CL_REG, 0x000, 0, 0x0, 0x0000},
2300 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2301 LD_SAP, 0x100, 3, 0x0, 0xffff},
2302 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
2303 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2304 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
2305 LD_LEN, 0x03e, 3, 0x0, 0xffff},
2306 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
2307 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2308 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
2309 LD_SUM, 0x015, 1, 0x0, 0x0000},
2310 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
2311 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2312 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2313 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2315 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2316 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2317 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2318 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2319 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2320 LD_R1, 0x205, 3, 0xB, 0xf000},
2321 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2322 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2323 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2324 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */
2325 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2326 LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2327 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2328 IM_CTL, 0x001, 3, 0x0, 0x0001},
2343 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2344 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2345 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2346 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */
2347 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2348 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2349 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2350 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */
2351 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2352 IM_CTL, 0x001, 3, 0x0, 0x0001},
2353 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2354 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
2368 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2369 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2370 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2371 IM_CTL, 0x04a, 3, 0x0, 0xffff},
2372 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2373 CL_REG, 0x000, 0, 0x0, 0x0000},
2374 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2375 CL_REG, 0x000, 0, 0x0, 0x0000},
2376 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2377 CL_REG, 0x000, 0, 0x0, 0x0000},
2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2379 CL_REG, 0x000, 0, 0x0, 0x0000},
2380 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2381 IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2382 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2383 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2384 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2385 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2386 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2387 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2388 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2389 LD_SUM, 0x015, 1, 0x0, 0x0000},
2390 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2391 IM_R1, 0x128, 1, 0x0, 0xffff},
2392 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2393 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2394 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2395 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2397 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2398 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2399 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2400 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2401 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2402 LD_R1, 0x205, 3, 0xB, 0xf000},
2403 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2404 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2405 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2406 IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
2407 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2408 IM_CTL, 0x001, 3, 0x0, 0x0001},
2418 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2419 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2420 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2421 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2422 #if 0
2424 //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2428 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2429 CL_REG, 0x000, 0, 0x0, 0x0000},
2430 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2431 CL_REG, 0x000, 0, 0x0, 0x0000},
2432 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2433 CL_REG, 0x000, 0, 0x0, 0x0000},
2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2435 CL_REG, 0x000, 0, 0x0, 0x0000},
2436 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2437 LD_SAP, 0x100, 3, 0x0, 0xffff},
2438 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2439 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2440 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2441 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2442 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2443 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2444 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2445 LD_SUM, 0x015, 1, 0x0, 0x0000},
2446 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2447 IM_R1, 0x128, 1, 0x0, 0xffff},
2448 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2449 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2451 #if 0
2452 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2454 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
2455 0x03f, 1, 0x0, 0xffff},
2457 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2458 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2459 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2460 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */
2461 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2462 LD_R1, 0x205, 3, 0xB, 0xf000} ,
2463 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2464 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2465 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2466 IM_CTL, 0x001, 3, 0x0, 0x0001},
2467 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2468 CL_REG, 0x002, 3, 0x0, 0x0000},
2469 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2470 IM_CTL, 0x080, 3, 0x0, 0xffff},
2471 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2472 IM_CTL, 0x044, 3, 0x0, 0xffff},
2474 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2475 0x021, 1, 0x0, 0xffff},
2477 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2478 0x021, 1, 0x0, 0xffff},
2480 #if 0
2481 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2483 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2484 0x021, 1, 0x0, 0xffff},
2486 #if 0
2487 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2489 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2490 0x021, 1, 0x0, 0xffff},
2504 #define CAS_PHY_UNKNOWN 0x00
2505 #define CAS_PHY_SERDES 0x01
2506 #define CAS_PHY_MII_MDIO0 0x02
2507 #define CAS_PHY_MII_MDIO1 0x04
2527 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2528 #error TX_DESC_RING_INDEX must be between 0 and 8
2531 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2532 #error RX_DESC_RING_INDEX must be between 0 and 8
2535 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2536 #error RX_COMP_RING_INDEX must be between 0 and 8
2542 #define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */
2569 #define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in
2570 bytes. 0 - 9256 */
2571 #define TX_DESC_BUFLEN_SHIFT 0
2572 #define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. #
2579 #define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff.
2585 #define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */
2586 #define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */
2587 #define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */
2588 #define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */
2589 #define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only.
2609 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2611 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2613 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2615 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2617 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2618 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2619 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2620 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2621 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2622 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2626 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2628 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2630 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2632 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2636 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2637 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2638 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2639 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2641 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2643 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2645 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2646 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2647 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2649 #define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */
2650 #define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */
2652 #define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */
2654 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2658 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2659 #define RX_COMP4_TCP_CSUM_SHIFT 0
2660 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2662 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2664 #define RX_COMP4_ZERO 0x0000080000000000ULL
2665 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2667 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2668 #define RX_COMP4_BAD 0x4000000000000000ULL
2669 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2675 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2676 #define RX_INDEX_NUM_SHIFT 0
2677 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2679 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2689 link_down = 0, /* No link, will retry */
2731 #define TX_TINY_BUF_LEN 0x100
2789 #define CAS_FLAG_1000MB_CAP 0x00000001
2790 #define CAS_FLAG_REG_PLUS 0x00000002
2791 #define CAS_FLAG_TARGET_ABORT 0x00000004
2792 #define CAS_FLAG_SATURN 0x00000008
2793 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2797 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2798 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2824 #if 0
2834 #define LINK_TRANSITION_UNKNOWN 0
2847 #define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */
2889 #define TX_TARGET_ABORT_LEN 0x20
2890 #define RX_SWIVEL_OFF_VAL 0x2
2893 #define RX_BLANK_INTR_PKT_VAL 0x05
2894 #define RX_BLANK_INTR_TIME_VAL 0x0F