4   Provides Bus interface for MII registers
16 #include <linux/mii.h>
84 	unsigned int mii_address = priv->hw->mii.addr;  in stmmac_xgmac2_mdio_read()
85 	unsigned int mii_data = priv->hw->mii.data;  in stmmac_xgmac2_mdio_read()
93 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_read()
100 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_xgmac2_mdio_read()
101 		& priv->hw->mii.clk_csr_mask;  in stmmac_xgmac2_mdio_read()
104 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_read()
111 	/* Set the MII address register to read */  in stmmac_xgmac2_mdio_read()
115 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_read()
122 	/* Read the data from the MII data register */  in stmmac_xgmac2_mdio_read()
167 	unsigned int mii_address = priv->hw->mii.addr;  in stmmac_xgmac2_mdio_write()
168 	unsigned int mii_data = priv->hw->mii.data;  in stmmac_xgmac2_mdio_write()
176 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_write()
183 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_xgmac2_mdio_write()
184 		& priv->hw->mii.clk_csr_mask;  in stmmac_xgmac2_mdio_write()
188 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_write()
195 	/* Set the MII address register to write */  in stmmac_xgmac2_mdio_write()
199 	/* Wait until any existing MII operation is complete */  in stmmac_xgmac2_mdio_write()
246 	unsigned int mii_address = priv->hw->mii.addr;  in stmmac_mdio_read()
247 	unsigned int mii_data = priv->hw->mii.data;  in stmmac_mdio_read()
261 	/* Read the data from the MII data register */  in stmmac_mdio_read()
268  * @phyaddr: MII addr
269  * @phyreg: MII reg
270  * Description: it reads data from the MII register from within the phy device.
271  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
286 	value |= (phyaddr << priv->hw->mii.addr_shift)  in stmmac_mdio_read_c22()
287 		& priv->hw->mii.addr_mask;  in stmmac_mdio_read_c22()
288 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_read_c22()
289 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_mdio_read_c22()
290 		& priv->hw->mii.clk_csr_mask;  in stmmac_mdio_read_c22()
304  * @phyaddr: MII addr
306  * @phyreg: MII reg
307  * Description: it reads data from the MII register from within the phy device.
308  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
326 	value |= (phyaddr << priv->hw->mii.addr_shift)  in stmmac_mdio_read_c45()
327 		& priv->hw->mii.addr_mask;  in stmmac_mdio_read_c45()
328 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_read_c45()
329 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_mdio_read_c45()
330 		& priv->hw->mii.clk_csr_mask;  in stmmac_mdio_read_c45()
333 	value &= ~priv->hw->mii.reg_mask;  in stmmac_mdio_read_c45()
334 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_read_c45()
347 	unsigned int mii_address = priv->hw->mii.addr;  in stmmac_mdio_write()
348 	unsigned int mii_data = priv->hw->mii.data;  in stmmac_mdio_write()
351 	/* Wait until any existing MII operation is complete */  in stmmac_mdio_write()
356 	/* Set the MII address register to write */  in stmmac_mdio_write()
360 	/* Wait until any existing MII operation is complete */  in stmmac_mdio_write()
368  * @phyaddr: MII addr
369  * @phyreg: MII reg
371  * Description: it writes the data into the MII register from within the device.
385 	value |= (phyaddr << priv->hw->mii.addr_shift)  in stmmac_mdio_write_c22()
386 		& priv->hw->mii.addr_mask;  in stmmac_mdio_write_c22()
387 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_write_c22()
389 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_mdio_write_c22()
390 		& priv->hw->mii.clk_csr_mask;  in stmmac_mdio_write_c22()
406  * @phyaddr: MII addr
407  * @phyreg: MII reg
410  * Description: it writes the data into the MII register from within the device.
426 	value |= (phyaddr << priv->hw->mii.addr_shift)  in stmmac_mdio_write_c45()
427 		& priv->hw->mii.addr_mask;  in stmmac_mdio_write_c45()
428 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_write_c45()
430 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)  in stmmac_mdio_write_c45()
431 		& priv->hw->mii.clk_csr_mask;  in stmmac_mdio_write_c45()
435 	value &= ~priv->hw->mii.reg_mask;  in stmmac_mdio_write_c45()
436 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;  in stmmac_mdio_write_c45()
450  * Description: reset the MII bus
457 	unsigned int mii_address = priv->hw->mii.addr;  in stmmac_mdio_reset()
519 		xpcs = xpcs_create_mdiodev(priv->mii, addr, mode);  in stmmac_pcs_setup()
550  * Description: it registers the MII bus
680 	priv->mii = new_bus;  in stmmac_mdio_register()
694  * Description: it unregisters the MII bus
700 	if (!priv->mii)  in stmmac_mdio_unregister()
703 	mdiobus_unregister(priv->mii);  in stmmac_mdio_unregister()
704 	priv->mii->priv = NULL;  in stmmac_mdio_unregister()
705 	mdiobus_free(priv->mii);  in stmmac_mdio_unregister()
706 	priv->mii = NULL;  in stmmac_mdio_unregister()