Lines Matching full:receive
18 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
95 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
101 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
102 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
111 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
112 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
113 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
115 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
137 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
141 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
144 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
145 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
146 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
147 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
149 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */