77 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_rx_chan()  local
81 	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_rx_chan()
83 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_rx_chan()
87 		       ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan));  in dwmac4_dma_init_rx_chan()
90 	       ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan));  in dwmac4_dma_init_rx_chan()
98 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_tx_chan()  local
102 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_tx_chan()
108 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_tx_chan()
112 		       ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan));  in dwmac4_dma_init_tx_chan()
115 	       ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan));  in dwmac4_dma_init_tx_chan()
122 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_channel()  local
126 	value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_channel()
129 	writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac4_dma_init_channel()
133 	       ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));  in dwmac4_dma_init_channel()
140 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac410_dma_init_channel()  local
144 	value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac410_dma_init_channel()
148 	writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac410_dma_init_channel()
152 	       ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));  in dwmac410_dma_init_channel()
194 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in _dwmac4_dump_dma_regs()  local
195 	const struct dwmac4_addrs *default_addrs = NULL;  in _dwmac4_dump_dma_regs()
201 		readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
203 		readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
205 		readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
207 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
209 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
211 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
213 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
215 		readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
217 		readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
219 		readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
221 		readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
223 		readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
225 		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
227 		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
229 		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
231 		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
233 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
235 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
237 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
239 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
241 		readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel));  in _dwmac4_dump_dma_regs()
256 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_rx_watchdog()  local
258 	writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));  in dwmac4_rx_watchdog()
265 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_rx_chan_op_mode()  local
269 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_dma_rx_chan_op_mode()
327 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_dma_rx_chan_op_mode()
334 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_tx_chan_op_mode()  local
335 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,  in dwmac4_dma_tx_chan_op_mode()
382 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_dma_tx_chan_op_mode()
483 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_tso()  local
488 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tso()
490 		       ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tso()
493 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tso()
495 		       ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tso()
502 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_qmode()  local
503 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,  in dwmac4_qmode()
512 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_qmode()
518 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_set_bfsize()  local
519 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));  in dwmac4_set_bfsize()
524 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));  in dwmac4_set_bfsize()
530 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_sph()  local
537 	value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_sph()
542 	writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_sph()
548 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_tbs()  local
549 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tbs()
556 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));  in dwmac4_enable_tbs()
558 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs,  in dwmac4_enable_tbs()