stmicro/stmmac/dwmac4.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
55 /* RX Queues Routing */
121 /* MAC RX Queue Enable */
126 /* MAC Flow Control RX */
129 /* RX Queues Priorities */
209 /* MAC config */
230 /* MAC extended config */
318 /*  MTL registers */
347 		addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);  in mtl_chanx_base_addr()
400 /* MTL ETS Control register */
410 		addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);  in mtl_etsx_ctrl_base_addr()
420 /* MTL Queue Quantum Weight */
430 		addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);  in mtl_txqx_weight_base_addr()
439 /* MTL sendSlopeCredit register */
449 		addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);  in mtl_send_slp_credx_base_addr()
458 /* MTL hiCredit register */
468 		addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);  in mtl_high_credx_base_addr()
477 /* MTL loCredit register */
487 		addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);  in mtl_low_credx_base_addr()
496 /*  MTL debug */
501 /* MTL debug: Tx FIFO Read Controller Status */
525 /*  MTL interrupt */
537 /*  MTL debug */
542 /* MTL debug: Tx FIFO Read Controller Status */