stmicro/stmmac/dwmac1000.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3   Copyright (C) 2007-2009  STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER	0x00000028	/* Wake-up Frame Filter */
37 #define	GMAC_INT_DISABLE_PCSLINK	BIT(1)
79 #define GMAC_ADDR_HIGH(reg)	((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg)	((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
83 #define GMAC_MAX_PERFECT_ADDRESSES	1
86 #define GMAC_RGSMIIIS		0x000000d8	/* RGMII/SMII status */
88 /* SGMII/RGMII status register */
90 #define GMAC_RGSMIIIS_SPEED		GENMASK(2, 1)
91 #define GMAC_RGSMIIIS_SPEED_SHIFT	1
105 #define GMAC_CONTROL_TC	0x01000000	/* Transmit Conf. in RGMII/SGMII */
116 #define GMAC_CONTROL_PS		0x00008000	/* Port Select 0:GMI 1:MII */
117 #define GMAC_CONTROL_FES	0x00004000	/* Speed 0:10 1:100 */
119 #define GMAC_CONTROL_LM		0x00001000	/* Loop-back mode */
144 /* GMII ADDR  defines */
164 #define GMAC_DEBUG_TRCSTS_READ	1
172 #define GMAC_DEBUG_TFCSTS_WAIT	1
175 /* MAC GMII or MII Transmit Protocol Engine Status */
177 #define GMAC_DEBUG_RXFSTS_MASK	GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
180 #define GMAC_DEBUG_RXFSTS_BT	1
186 #define GMAC_DEBUG_RRCSTS_RDATA	1
191 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
192 #define GMAC_DEBUG_RFCFCSTS_SHIFT	1
193 /* MAC GMII or MII Receive Protocol Engine Status */
196 /*--- DMA BLOCK defines ---*/
207 	double_ratio = 0x00004000,	/* 2:1 */
208 	triple_ratio = 0x00008000,	/* 3:1 */
209 	quadruple_ratio = 0x0000c000,	/* 4:1 */
214 #define DMA_BUS_MODE_RPBL_MASK	0x007e0000	/* Rx-Programmable Burst Len */
278  *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
279  *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
280  *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
281  *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
282  *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
283  *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
284  *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
285  *   1,11 - Reserved
291  * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
295  * is set to 0. This allows pause frames with a quanta of 0 to be sent
296  * as an XOFF message to the link peer.