Lines Matching refs:REG_ETHER_CLOCK_SEL
20 #define REG_ETHER_CLOCK_SEL 0x52D0 macro
99 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
102 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
108 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
111 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
114 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
120 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
123 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
126 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
132 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
135 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_fix_mac_speed()
170 writel(clk_sel_val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_init_hw()
173 dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_init_hw()