Lines Matching +full:tx +full:- +full:use +full:- +full:rgmii +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
12 #include <linux/clk.h>
72 struct clk *clk_mac;
73 struct clk *clk_phy;
90 #define DELAY_ENABLE(soc, tx, rx) \ argument
91 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
104 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
106 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
111 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
117 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in px30_set_rmii_speed()
118 struct device *dev = &bsp_priv->pdev->dev; in px30_set_rmii_speed()
127 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_rmii_speed()
135 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_rmii_speed()
184 struct device *dev = &bsp_priv->pdev->dev; in rk3128_set_to_rgmii()
186 if (IS_ERR(bsp_priv->grf)) { in rk3128_set_to_rgmii()
191 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_to_rgmii()
194 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, in rk3128_set_to_rgmii()
202 struct device *dev = &bsp_priv->pdev->dev; in rk3128_set_to_rmii()
204 if (IS_ERR(bsp_priv->grf)) { in rk3128_set_to_rmii()
209 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_to_rmii()
215 struct device *dev = &bsp_priv->pdev->dev; in rk3128_set_rgmii_speed()
217 if (IS_ERR(bsp_priv->grf)) { in rk3128_set_rgmii_speed()
223 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_rgmii_speed()
226 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_rgmii_speed()
229 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_rgmii_speed()
232 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3128_set_rgmii_speed()
237 struct device *dev = &bsp_priv->pdev->dev; in rk3128_set_rmii_speed()
239 if (IS_ERR(bsp_priv->grf)) { in rk3128_set_rmii_speed()
245 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_rmii_speed()
249 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_rmii_speed()
300 struct device *dev = &bsp_priv->pdev->dev; in rk3228_set_to_rgmii()
302 if (IS_ERR(bsp_priv->grf)) { in rk3228_set_to_rgmii()
307 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_to_rgmii()
312 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, in rk3228_set_to_rgmii()
319 struct device *dev = &bsp_priv->pdev->dev; in rk3228_set_to_rmii()
321 if (IS_ERR(bsp_priv->grf)) { in rk3228_set_to_rmii()
326 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_to_rmii()
331 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); in rk3228_set_to_rmii()
336 struct device *dev = &bsp_priv->pdev->dev; in rk3228_set_rgmii_speed()
338 if (IS_ERR(bsp_priv->grf)) { in rk3228_set_rgmii_speed()
344 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_rgmii_speed()
347 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_rgmii_speed()
350 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_rgmii_speed()
353 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3228_set_rgmii_speed()
358 struct device *dev = &bsp_priv->pdev->dev; in rk3228_set_rmii_speed()
360 if (IS_ERR(bsp_priv->grf)) { in rk3228_set_rmii_speed()
366 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_rmii_speed()
370 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_rmii_speed()
379 regmap_write(priv->grf, RK3228_GRF_CON_MUX, in rk3228_integrated_phy_powerup()
422 struct device *dev = &bsp_priv->pdev->dev; in rk3288_set_to_rgmii()
424 if (IS_ERR(bsp_priv->grf)) { in rk3288_set_to_rgmii()
429 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_to_rgmii()
432 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, in rk3288_set_to_rgmii()
440 struct device *dev = &bsp_priv->pdev->dev; in rk3288_set_to_rmii()
442 if (IS_ERR(bsp_priv->grf)) { in rk3288_set_to_rmii()
447 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_to_rmii()
453 struct device *dev = &bsp_priv->pdev->dev; in rk3288_set_rgmii_speed()
455 if (IS_ERR(bsp_priv->grf)) { in rk3288_set_rgmii_speed()
461 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_rgmii_speed()
464 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_rgmii_speed()
467 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_rgmii_speed()
470 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3288_set_rgmii_speed()
475 struct device *dev = &bsp_priv->pdev->dev; in rk3288_set_rmii_speed()
477 if (IS_ERR(bsp_priv->grf)) { in rk3288_set_rmii_speed()
483 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_rmii_speed()
487 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_rmii_speed()
514 struct device *dev = &bsp_priv->pdev->dev; in rk3308_set_to_rmii()
516 if (IS_ERR(bsp_priv->grf)) { in rk3308_set_to_rmii()
521 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, in rk3308_set_to_rmii()
527 struct device *dev = &bsp_priv->pdev->dev; in rk3308_set_rmii_speed()
529 if (IS_ERR(bsp_priv->grf)) { in rk3308_set_rmii_speed()
535 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, in rk3308_set_rmii_speed()
538 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, in rk3308_set_rmii_speed()
586 struct device *dev = &bsp_priv->pdev->dev; in rk3328_set_to_rgmii()
588 if (IS_ERR(bsp_priv->grf)) { in rk3328_set_to_rgmii()
593 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, in rk3328_set_to_rgmii()
599 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, in rk3328_set_to_rgmii()
606 struct device *dev = &bsp_priv->pdev->dev; in rk3328_set_to_rmii()
609 if (IS_ERR(bsp_priv->grf)) { in rk3328_set_to_rmii()
614 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : in rk3328_set_to_rmii()
617 regmap_write(bsp_priv->grf, reg, in rk3328_set_to_rmii()
624 struct device *dev = &bsp_priv->pdev->dev; in rk3328_set_rgmii_speed()
626 if (IS_ERR(bsp_priv->grf)) { in rk3328_set_rgmii_speed()
632 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, in rk3328_set_rgmii_speed()
635 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, in rk3328_set_rgmii_speed()
638 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, in rk3328_set_rgmii_speed()
641 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3328_set_rgmii_speed()
646 struct device *dev = &bsp_priv->pdev->dev; in rk3328_set_rmii_speed()
649 if (IS_ERR(bsp_priv->grf)) { in rk3328_set_rmii_speed()
654 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : in rk3328_set_rmii_speed()
658 regmap_write(bsp_priv->grf, reg, in rk3328_set_rmii_speed()
662 regmap_write(bsp_priv->grf, reg, in rk3328_set_rmii_speed()
671 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, in rk3328_integrated_phy_powerup()
714 struct device *dev = &bsp_priv->pdev->dev; in rk3366_set_to_rgmii()
716 if (IS_ERR(bsp_priv->grf)) { in rk3366_set_to_rgmii()
721 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_to_rgmii()
724 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, in rk3366_set_to_rgmii()
732 struct device *dev = &bsp_priv->pdev->dev; in rk3366_set_to_rmii()
734 if (IS_ERR(bsp_priv->grf)) { in rk3366_set_to_rmii()
739 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_to_rmii()
745 struct device *dev = &bsp_priv->pdev->dev; in rk3366_set_rgmii_speed()
747 if (IS_ERR(bsp_priv->grf)) { in rk3366_set_rgmii_speed()
753 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_rgmii_speed()
756 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_rgmii_speed()
759 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_rgmii_speed()
762 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3366_set_rgmii_speed()
767 struct device *dev = &bsp_priv->pdev->dev; in rk3366_set_rmii_speed()
769 if (IS_ERR(bsp_priv->grf)) { in rk3366_set_rmii_speed()
775 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_rmii_speed()
779 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_rmii_speed()
825 struct device *dev = &bsp_priv->pdev->dev; in rk3368_set_to_rgmii()
827 if (IS_ERR(bsp_priv->grf)) { in rk3368_set_to_rgmii()
832 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_to_rgmii()
835 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, in rk3368_set_to_rgmii()
843 struct device *dev = &bsp_priv->pdev->dev; in rk3368_set_to_rmii()
845 if (IS_ERR(bsp_priv->grf)) { in rk3368_set_to_rmii()
850 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_to_rmii()
856 struct device *dev = &bsp_priv->pdev->dev; in rk3368_set_rgmii_speed()
858 if (IS_ERR(bsp_priv->grf)) { in rk3368_set_rgmii_speed()
864 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_rgmii_speed()
867 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_rgmii_speed()
870 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_rgmii_speed()
873 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3368_set_rgmii_speed()
878 struct device *dev = &bsp_priv->pdev->dev; in rk3368_set_rmii_speed()
880 if (IS_ERR(bsp_priv->grf)) { in rk3368_set_rmii_speed()
886 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_rmii_speed()
890 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_rmii_speed()
936 struct device *dev = &bsp_priv->pdev->dev; in rk3399_set_to_rgmii()
938 if (IS_ERR(bsp_priv->grf)) { in rk3399_set_to_rgmii()
943 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_to_rgmii()
946 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, in rk3399_set_to_rgmii()
954 struct device *dev = &bsp_priv->pdev->dev; in rk3399_set_to_rmii()
956 if (IS_ERR(bsp_priv->grf)) { in rk3399_set_to_rmii()
961 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_to_rmii()
967 struct device *dev = &bsp_priv->pdev->dev; in rk3399_set_rgmii_speed()
969 if (IS_ERR(bsp_priv->grf)) { in rk3399_set_rgmii_speed()
975 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_rgmii_speed()
978 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_rgmii_speed()
981 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_rgmii_speed()
984 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); in rk3399_set_rgmii_speed()
989 struct device *dev = &bsp_priv->pdev->dev; in rk3399_set_rmii_speed()
991 if (IS_ERR(bsp_priv->grf)) { in rk3399_set_rmii_speed()
997 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_rmii_speed()
1001 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_rmii_speed()
1040 struct device *dev = &bsp_priv->pdev->dev; in rk3568_set_to_rgmii()
1043 if (IS_ERR(bsp_priv->grf)) { in rk3568_set_to_rgmii()
1048 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : in rk3568_set_to_rgmii()
1050 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : in rk3568_set_to_rgmii()
1053 regmap_write(bsp_priv->grf, con0, in rk3568_set_to_rgmii()
1057 regmap_write(bsp_priv->grf, con1, in rk3568_set_to_rgmii()
1065 struct device *dev = &bsp_priv->pdev->dev; in rk3568_set_to_rmii()
1068 if (IS_ERR(bsp_priv->grf)) { in rk3568_set_to_rmii()
1073 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : in rk3568_set_to_rmii()
1075 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); in rk3568_set_to_rmii()
1080 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in rk3568_set_gmac_speed()
1081 struct device *dev = &bsp_priv->pdev->dev; in rk3568_set_gmac_speed()
1159 struct device *dev = &bsp_priv->pdev->dev; in rk3576_set_to_rgmii()
1162 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { in rk3576_set_to_rgmii()
1163 dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n"); in rk3576_set_to_rgmii()
1167 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_to_rgmii()
1170 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); in rk3576_set_to_rgmii()
1172 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : in rk3576_set_to_rgmii()
1176 regmap_write(bsp_priv->php_grf, offset_con, in rk3576_set_to_rgmii()
1178 regmap_write(bsp_priv->php_grf, offset_con + 0x4, in rk3576_set_to_rgmii()
1182 regmap_write(bsp_priv->php_grf, offset_con, in rk3576_set_to_rgmii()
1185 regmap_write(bsp_priv->php_grf, offset_con + 0x4, in rk3576_set_to_rgmii()
1192 struct device *dev = &bsp_priv->pdev->dev; in rk3576_set_to_rmii()
1195 if (IS_ERR(bsp_priv->grf)) { in rk3576_set_to_rmii()
1200 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_to_rmii()
1203 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); in rk3576_set_to_rmii()
1208 struct device *dev = &bsp_priv->pdev->dev; in rk3576_set_gmac_speed()
1213 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) in rk3576_set_gmac_speed()
1219 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) in rk3576_set_gmac_speed()
1225 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) in rk3576_set_gmac_speed()
1234 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_gmac_speed()
1237 regmap_write(bsp_priv->grf, offset_con, val); in rk3576_set_gmac_speed()
1254 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_clock_selection()
1257 regmap_write(bsp_priv->grf, offset_con, val); in rk3576_set_clock_selection()
1318 struct device *dev = &bsp_priv->pdev->dev; in rk3588_set_to_rgmii()
1319 u32 offset_con, id = bsp_priv->id; in rk3588_set_to_rgmii()
1321 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { in rk3588_set_to_rgmii()
1326 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : in rk3588_set_to_rgmii()
1329 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, in rk3588_set_to_rgmii()
1332 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, in rk3588_set_to_rgmii()
1335 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, in rk3588_set_to_rgmii()
1339 regmap_write(bsp_priv->grf, offset_con, in rk3588_set_to_rgmii()
1346 struct device *dev = &bsp_priv->pdev->dev; in rk3588_set_to_rmii()
1348 if (IS_ERR(bsp_priv->php_grf)) { in rk3588_set_to_rmii()
1353 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, in rk3588_set_to_rmii()
1354 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); in rk3588_set_to_rmii()
1356 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, in rk3588_set_to_rmii()
1357 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); in rk3588_set_to_rmii()
1362 struct device *dev = &bsp_priv->pdev->dev; in rk3588_set_gmac_speed()
1363 unsigned int val = 0, id = bsp_priv->id; in rk3588_set_gmac_speed()
1367 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) in rk3588_set_gmac_speed()
1373 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) in rk3588_set_gmac_speed()
1379 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) in rk3588_set_gmac_speed()
1388 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); in rk3588_set_gmac_speed()
1398 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : in rk3588_set_clock_selection()
1399 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); in rk3588_set_clock_selection()
1401 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : in rk3588_set_clock_selection()
1402 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); in rk3588_set_clock_selection()
1404 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); in rk3588_set_clock_selection()
1435 struct device *dev = &bsp_priv->pdev->dev; in rv1108_set_to_rmii()
1437 if (IS_ERR(bsp_priv->grf)) { in rv1108_set_to_rmii()
1442 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, in rv1108_set_to_rmii()
1448 struct device *dev = &bsp_priv->pdev->dev; in rv1108_set_rmii_speed()
1450 if (IS_ERR(bsp_priv->grf)) { in rv1108_set_rmii_speed()
1456 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, in rv1108_set_rmii_speed()
1460 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, in rv1108_set_rmii_speed()
1503 struct device *dev = &bsp_priv->pdev->dev; in rv1126_set_to_rgmii()
1505 if (IS_ERR(bsp_priv->grf)) { in rv1126_set_to_rgmii()
1510 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, in rv1126_set_to_rgmii()
1517 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, in rv1126_set_to_rgmii()
1521 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, in rv1126_set_to_rgmii()
1528 struct device *dev = &bsp_priv->pdev->dev; in rv1126_set_to_rmii()
1530 if (IS_ERR(bsp_priv->grf)) { in rv1126_set_to_rmii()
1535 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, in rv1126_set_to_rmii()
1541 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in rv1126_set_rgmii_speed()
1542 struct device *dev = &bsp_priv->pdev->dev; in rv1126_set_rgmii_speed()
1557 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); in rv1126_set_rgmii_speed()
1569 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in rv1126_set_rmii_speed()
1570 struct device *dev = &bsp_priv->pdev->dev; in rv1126_set_rmii_speed()
1582 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); in rv1126_set_rmii_speed()
1613 if (priv->ops->integrated_phy_powerup) in rk_gmac_integrated_phy_powerup()
1614 priv->ops->integrated_phy_powerup(priv); in rk_gmac_integrated_phy_powerup()
1616 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); in rk_gmac_integrated_phy_powerup()
1617 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); in rk_gmac_integrated_phy_powerup()
1619 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); in rk_gmac_integrated_phy_powerup()
1620 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); in rk_gmac_integrated_phy_powerup()
1622 if (priv->phy_reset) { in rk_gmac_integrated_phy_powerup()
1624 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_phy_powerup()
1625 if (priv->phy_reset) in rk_gmac_integrated_phy_powerup()
1626 reset_control_assert(priv->phy_reset); in rk_gmac_integrated_phy_powerup()
1628 if (priv->phy_reset) in rk_gmac_integrated_phy_powerup()
1629 reset_control_deassert(priv->phy_reset); in rk_gmac_integrated_phy_powerup()
1631 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); in rk_gmac_integrated_phy_powerup()
1638 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_phy_powerdown()
1639 if (priv->phy_reset) in rk_gmac_integrated_phy_powerdown()
1640 reset_control_assert(priv->phy_reset); in rk_gmac_integrated_phy_powerdown()
1645 struct rk_priv_data *bsp_priv = plat->bsp_priv; in rk_gmac_clk_init()
1646 struct device *dev = &bsp_priv->pdev->dev; in rk_gmac_clk_init()
1647 int phy_iface = bsp_priv->phy_iface; in rk_gmac_clk_init()
1650 bsp_priv->clk_enabled = false; in rk_gmac_clk_init()
1652 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); in rk_gmac_clk_init()
1654 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); in rk_gmac_clk_init()
1656 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, in rk_gmac_clk_init()
1657 sizeof(*bsp_priv->clks), GFP_KERNEL); in rk_gmac_clk_init()
1658 if (!bsp_priv->clks) in rk_gmac_clk_init()
1659 return -ENOMEM; in rk_gmac_clk_init()
1662 bsp_priv->clks[i].id = rk_clocks[i]; in rk_gmac_clk_init()
1666 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; in rk_gmac_clk_init()
1669 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, in rk_gmac_clk_init()
1670 bsp_priv->clks); in rk_gmac_clk_init()
1675 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); in rk_gmac_clk_init()
1676 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac); in rk_gmac_clk_init()
1680 if (bsp_priv->clock_input) { in rk_gmac_clk_init()
1683 clk_set_rate(bsp_priv->clk_mac, 50000000); in rk_gmac_clk_init()
1686 if (plat->phy_node && bsp_priv->integrated_phy) { in rk_gmac_clk_init()
1687 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); in rk_gmac_clk_init()
1688 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); in rk_gmac_clk_init()
1691 clk_set_rate(bsp_priv->clk_phy, 50000000); in rk_gmac_clk_init()
1702 if (!bsp_priv->clk_enabled) { in gmac_clk_enable()
1703 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, in gmac_clk_enable()
1704 bsp_priv->clks); in gmac_clk_enable()
1708 ret = clk_prepare_enable(bsp_priv->clk_phy); in gmac_clk_enable()
1712 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) in gmac_clk_enable()
1713 bsp_priv->ops->set_clock_selection(bsp_priv, in gmac_clk_enable()
1714 bsp_priv->clock_input, true); in gmac_clk_enable()
1717 bsp_priv->clk_enabled = true; in gmac_clk_enable()
1720 if (bsp_priv->clk_enabled) { in gmac_clk_enable()
1721 clk_bulk_disable_unprepare(bsp_priv->num_clks, in gmac_clk_enable()
1722 bsp_priv->clks); in gmac_clk_enable()
1723 clk_disable_unprepare(bsp_priv->clk_phy); in gmac_clk_enable()
1725 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) in gmac_clk_enable()
1726 bsp_priv->ops->set_clock_selection(bsp_priv, in gmac_clk_enable()
1727 bsp_priv->clock_input, false); in gmac_clk_enable()
1729 bsp_priv->clk_enabled = false; in gmac_clk_enable()
1738 struct regulator *ldo = bsp_priv->regulator; in phy_power_on()
1740 struct device *dev = &bsp_priv->pdev->dev; in phy_power_on()
1745 dev_err(dev, "fail to enable phy-supply\n"); in phy_power_on()
1749 dev_err(dev, "fail to disable phy-supply\n"); in phy_power_on()
1760 struct device *dev = &pdev->dev; in rk_gmac_setup()
1768 return ERR_PTR(-ENOMEM); in rk_gmac_setup()
1770 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface); in rk_gmac_setup()
1771 bsp_priv->ops = ops; in rk_gmac_setup()
1777 if (res && ops->regs_valid) { in rk_gmac_setup()
1780 while (ops->regs[i]) { in rk_gmac_setup()
1781 if (ops->regs[i] == res->start) { in rk_gmac_setup()
1782 bsp_priv->id = i; in rk_gmac_setup()
1789 bsp_priv->regulator = devm_regulator_get(dev, "phy"); in rk_gmac_setup()
1790 if (IS_ERR(bsp_priv->regulator)) { in rk_gmac_setup()
1791 ret = PTR_ERR(bsp_priv->regulator); in rk_gmac_setup()
1796 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); in rk_gmac_setup()
1799 bsp_priv->clock_input = true; in rk_gmac_setup()
1804 bsp_priv->clock_input = true; in rk_gmac_setup()
1806 bsp_priv->clock_input = false; in rk_gmac_setup()
1809 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); in rk_gmac_setup()
1811 bsp_priv->tx_delay = 0x30; in rk_gmac_setup()
1814 bsp_priv->tx_delay); in rk_gmac_setup()
1816 dev_info(dev, "TX delay(0x%x).\n", value); in rk_gmac_setup()
1817 bsp_priv->tx_delay = value; in rk_gmac_setup()
1820 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); in rk_gmac_setup()
1822 bsp_priv->rx_delay = 0x10; in rk_gmac_setup()
1825 bsp_priv->rx_delay); in rk_gmac_setup()
1828 bsp_priv->rx_delay = value; in rk_gmac_setup()
1831 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rk_gmac_setup()
1833 bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rk_gmac_setup()
1834 "rockchip,php-grf"); in rk_gmac_setup()
1836 if (plat->phy_node) { in rk_gmac_setup()
1837 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, in rk_gmac_setup()
1838 "phy-is-integrated"); in rk_gmac_setup()
1839 if (bsp_priv->integrated_phy) { in rk_gmac_setup()
1840 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); in rk_gmac_setup()
1841 if (IS_ERR(bsp_priv->phy_reset)) { in rk_gmac_setup()
1842 dev_err(&pdev->dev, "No PHY reset control found.\n"); in rk_gmac_setup()
1843 bsp_priv->phy_reset = NULL; in rk_gmac_setup()
1848 bsp_priv->integrated_phy ? "yes" : "no"); in rk_gmac_setup()
1850 bsp_priv->pdev = pdev; in rk_gmac_setup()
1857 switch (bsp_priv->phy_iface) { in rk_gmac_check_ops()
1862 if (!bsp_priv->ops->set_to_rgmii) in rk_gmac_check_ops()
1863 return -EINVAL; in rk_gmac_check_ops()
1866 if (!bsp_priv->ops->set_to_rmii) in rk_gmac_check_ops()
1867 return -EINVAL; in rk_gmac_check_ops()
1870 dev_err(&bsp_priv->pdev->dev, in rk_gmac_check_ops()
1871 "unsupported interface %d", bsp_priv->phy_iface); in rk_gmac_check_ops()
1879 struct device *dev = &bsp_priv->pdev->dev; in rk_gmac_powerup()
1889 /*rmii or rgmii*/ in rk_gmac_powerup()
1890 switch (bsp_priv->phy_iface) { in rk_gmac_powerup()
1892 dev_info(dev, "init for RGMII\n"); in rk_gmac_powerup()
1893 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, in rk_gmac_powerup()
1894 bsp_priv->rx_delay); in rk_gmac_powerup()
1898 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); in rk_gmac_powerup()
1902 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); in rk_gmac_powerup()
1906 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); in rk_gmac_powerup()
1910 bsp_priv->ops->set_to_rmii(bsp_priv); in rk_gmac_powerup()
1924 if (bsp_priv->integrated_phy) in rk_gmac_powerup()
1932 if (gmac->integrated_phy) in rk_gmac_powerdown()
1935 pm_runtime_put_sync(&gmac->pdev->dev); in rk_gmac_powerdown()
1944 struct device *dev = &bsp_priv->pdev->dev; in rk_fix_speed()
1946 switch (bsp_priv->phy_iface) { in rk_fix_speed()
1951 if (bsp_priv->ops->set_rgmii_speed) in rk_fix_speed()
1952 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); in rk_fix_speed()
1955 if (bsp_priv->ops->set_rmii_speed) in rk_fix_speed()
1956 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); in rk_fix_speed()
1959 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); in rk_fix_speed()
1970 data = of_device_get_match_data(&pdev->dev); in rk_gmac_probe()
1972 dev_err(&pdev->dev, "no of match data provided\n"); in rk_gmac_probe()
1973 return -EINVAL; in rk_gmac_probe()
1987 if (!plat_dat->has_gmac4) in rk_gmac_probe()
1988 plat_dat->has_gmac = true; in rk_gmac_probe()
1989 plat_dat->fix_mac_speed = rk_fix_speed; in rk_gmac_probe()
1991 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); in rk_gmac_probe()
1992 if (IS_ERR(plat_dat->bsp_priv)) in rk_gmac_probe()
1993 return PTR_ERR(plat_dat->bsp_priv); in rk_gmac_probe()
1999 ret = rk_gmac_powerup(plat_dat->bsp_priv); in rk_gmac_probe()
2003 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in rk_gmac_probe()
2010 rk_gmac_powerdown(plat_dat->bsp_priv); in rk_gmac_probe()
2017 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); in rk_gmac_remove()
2019 stmmac_dvr_remove(&pdev->dev); in rk_gmac_remove()
2030 /* Keep the PHY up if we use Wake-on-Lan. */ in rk_gmac_suspend()
2033 bsp_priv->suspended = true; in rk_gmac_suspend()
2043 /* The PHY was up for Wake-on-Lan. */ in rk_gmac_resume()
2044 if (bsp_priv->suspended) { in rk_gmac_resume()
2046 bsp_priv->suspended = false; in rk_gmac_resume()
2056 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
2057 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2058 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2059 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2060 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
2061 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2062 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2063 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2064 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2065 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2066 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
2067 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2068 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2069 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2078 .name = "rk_gmac-dwmac",
2085 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");