Lines Matching +full:0 +full:x1800000
14 #define RGMII_IO_MACRO_CONFIG 0x0
15 #define SDCC_HC_REG_DLL_CONFIG 0x4
16 #define SDCC_TEST_CTL 0x8
17 #define SDCC_HC_REG_DDR_CONFIG 0xC
18 #define SDCC_HC_REG_DLL_CONFIG2 0x10
19 #define SDC4_STATUS 0x14
20 #define SDCC_USR_CTL 0x18
21 #define RGMII_IO_MACRO_CONFIG2 0x1C
22 #define RGMII_IO_MACRO_DEBUG1 0x20
23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
24 #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4
37 #define RGMII_CONFIG_DDR_MODE BIT(0)
58 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
65 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
86 #define SGMII_10M_RX_CLK_DVDR 0x31
209 enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0, in qcom_ethqos_set_sgmii_loopback()
221 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
222 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
223 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
224 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
225 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
226 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
237 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
238 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
239 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
240 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
241 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
242 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
253 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
254 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
255 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
256 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
257 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
258 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
267 .dma_chan = 0x00008100,
268 .dma_chan_offset = 0x1000,
269 .mtl_chan = 0x00008000,
270 .mtl_chan_offset = 0x1000,
271 .mtl_ets_ctrl = 0x00008010,
272 .mtl_ets_ctrl_offset = 0x1000,
273 .mtl_txq_weight = 0x00008018,
274 .mtl_txq_weight_offset = 0x1000,
275 .mtl_send_slp_cred = 0x0000801c,
276 .mtl_send_slp_cred_offset = 0x1000,
277 .mtl_high_cred = 0x00008020,
278 .mtl_high_cred_offset = 0x1000,
279 .mtl_low_cred = 0x00008024,
280 .mtl_low_cred_offset = 0x1000,
285 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
286 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
287 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
288 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
289 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
290 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
303 .dma_chan = 0x00008100,
304 .dma_chan_offset = 0x1000,
305 .mtl_chan = 0x00008000,
306 .mtl_chan_offset = 0x1000,
307 .mtl_ets_ctrl = 0x00008010,
308 .mtl_ets_ctrl_offset = 0x1000,
309 .mtl_txq_weight = 0x00008018,
310 .mtl_txq_weight_offset = 0x1000,
311 .mtl_send_slp_cred = 0x0000801c,
312 .mtl_send_slp_cred_offset = 0x1000,
313 .mtl_high_cred = 0x00008020,
314 .mtl_high_cred_offset = 0x1000,
315 .mtl_low_cred = 0x00008024,
316 .mtl_low_cred_offset = 0x1000,
336 0, SDCC_HC_REG_DLL_CONFIG); in ethqos_dll_configure()
344 0, SDCC_HC_REG_DLL_CONFIG); in ethqos_dll_configure()
347 0, SDCC_HC_REG_DLL_CONFIG); in ethqos_dll_configure()
358 } while (retry > 0); in ethqos_dll_configure()
375 } while (retry > 0); in ethqos_dll_configure()
385 0, SDCC_HC_REG_DLL_CONFIG2); in ethqos_dll_configure()
388 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); in ethqos_dll_configure()
398 return 0; in ethqos_dll_configure()
410 phase_shift = 0; in ethqos_rgmii_macro_init()
416 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
422 loopback = 0; in ethqos_rgmii_macro_init()
424 /* Select RGMII, write 0 to interface select */ in ethqos_rgmii_macro_init()
426 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
433 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
440 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
445 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
476 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
478 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
480 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
486 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
494 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
496 /* Write 0x5 to PRG_RCLK_DLY_CODE */ in ethqos_rgmii_macro_init()
516 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
518 0, RGMII_IO_MACRO_CONFIG); in ethqos_rgmii_macro_init()
520 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
527 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
534 0, RGMII_IO_MACRO_CONFIG2); in ethqos_rgmii_macro_init()
535 /* Write 0x5 to PRG_RCLK_DLY_CODE */ in ethqos_rgmii_macro_init()
552 return 0; in ethqos_rgmii_macro_init()
562 for (i = 0; i < ethqos->num_por; i++) in ethqos_configure_rgmii()
579 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); in ethqos_configure_rgmii()
580 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); in ethqos_configure_rgmii()
581 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); in ethqos_configure_rgmii()
583 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); in ethqos_configure_rgmii()
584 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); in ethqos_configure_rgmii()
589 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, in ethqos_configure_rgmii()
593 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, in ethqos_configure_rgmii()
618 } while (retry > 0); in ethqos_configure_rgmii()
628 return 0; in ethqos_configure_rgmii()
657 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 0, 0, 0); in ethqos_configure_sgmii()
665 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); in ethqos_configure_sgmii()
670 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); in ethqos_configure_sgmii()
680 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); in ethqos_configure_sgmii()
739 int ret = 0; in ethqos_clks_config()