Lines Matching +full:2 +full:rgmii
28 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
36 * cycle of the 125MHz RGMII TX clock):
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
74 * Each step is 200ps. These bits are used with external RGMII PHYs
75 * because RGMII RX only has the small window. cfg_rxclk_dly can
152 { .div = 2, .val = 2, }, in meson8b_init_rgmii_tx_clk()
192 clk_configs->fixed_div2.div = 2; in meson8b_init_rgmii_tx_clk()
220 /* enable RGMII mode */ in meson8b_set_phy_mode()
226 /* disable RGMII mode -> enables RMII mode */ in meson8b_set_phy_mode()
246 /* enable RGMII mode */ in meson_axg_set_phy_mode()
252 /* disable RGMII mode -> enables RMII mode */ in meson_axg_set_phy_mode()
355 /* only relevant for RMII mode -> disable in RGMII mode */ in meson8b_init_prg_eth()
359 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
367 "failed to set RGMII TX clock\n"); in meson8b_init_prg_eth()
375 "failed to enable the RGMII TX clock\n"); in meson8b_init_prg_eth()
426 /* use 2ns as fallback since this value was previously hardcoded */ in meson8b_dwmac_probe()
429 dwmac->tx_delay_ns = 2; in meson8b_dwmac_probe()
444 "The RGMII RX delay range is 0..3000ps in 200ps steps"); in meson8b_dwmac_probe()
450 "The only allowed RGMII RX delays values are: 0ps, 2000ps"); in meson8b_dwmac_probe()