Lines Matching +full:tx +full:- +full:clk +full:- +full:delay +full:- +full:ps
1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
149 /* 550ps per stage for MII/RMII */ in mt2712_delay_ps2stage()
150 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage()
151 mac_delay->rx_delay /= 550; in mt2712_delay_ps2stage()
157 /* 170ps per stage for RGMII */ in mt2712_delay_ps2stage()
158 mac_delay->tx_delay /= 170; in mt2712_delay_ps2stage()
159 mac_delay->rx_delay /= 170; in mt2712_delay_ps2stage()
162 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_ps2stage()
169 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_stage2ps()
171 switch (plat->phy_mode) { in mt2712_delay_stage2ps()
174 /* 550ps per stage for MII/RMII */ in mt2712_delay_stage2ps()
175 mac_delay->tx_delay *= 550; in mt2712_delay_stage2ps()
176 mac_delay->rx_delay *= 550; in mt2712_delay_stage2ps()
182 /* 170ps per stage for RGMII */ in mt2712_delay_stage2ps()
183 mac_delay->tx_delay *= 170; in mt2712_delay_stage2ps()
184 mac_delay->rx_delay *= 170; in mt2712_delay_stage2ps()
187 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_stage2ps()
194 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_set_delay()
199 switch (plat->phy_mode) { in mt2712_set_delay()
201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
203 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
205 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
206 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
207 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
210 if (plat->rmii_clk_from_mac) { in mt2712_set_delay()
213 * The egress timing can be adjusted by GTXC delay macro circuit. in mt2712_set_delay()
214 * The ingress timing can be adjusted by TXC delay macro circuit. in mt2712_set_delay()
216 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
217 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
218 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
220 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
221 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
222 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
226 * the reference clk is connected to. The reference clock is a in mt2712_set_delay()
230 if (plat->rmii_rxc) { in mt2712_set_delay()
233 * by RXC delay macro circuit. in mt2712_set_delay()
235 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
236 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
237 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
241 * by TXC delay macro circuit. in mt2712_set_delay()
243 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
244 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
245 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
247 /* tx_inv will inverse the tx clock inside mac relateive to in mt2712_set_delay()
249 * and this bit is located in the same register with fine-tune in mt2712_set_delay()
251 if (mac_delay->tx_inv) in mt2712_set_delay()
261 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
262 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
263 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
265 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
266 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
267 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
270 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_delay()
271 return -EINVAL; in mt2712_set_delay()
273 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); in mt2712_set_delay()
274 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); in mt2712_set_delay()
293 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0; in mt8195_set_interface()
294 int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0; in mt8195_set_interface()
298 switch (plat->phy_mode) { in mt8195_set_interface()
313 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_interface()
314 return -EINVAL; in mt8195_set_interface()
320 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); in mt8195_set_interface()
327 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_ps2stage()
329 /* 290ps per stage */ in mt8195_delay_ps2stage()
330 mac_delay->tx_delay /= 290; in mt8195_delay_ps2stage()
331 mac_delay->rx_delay /= 290; in mt8195_delay_ps2stage()
336 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_stage2ps()
338 /* 290ps per stage */ in mt8195_delay_stage2ps()
339 mac_delay->tx_delay *= 290; in mt8195_delay_stage2ps()
340 mac_delay->rx_delay *= 290; in mt8195_delay_stage2ps()
345 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_set_delay()
350 switch (plat->phy_mode) { in mt8195_set_delay()
352 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
353 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
354 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv); in mt8195_set_delay()
356 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt8195_set_delay()
357 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); in mt8195_set_delay()
358 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); in mt8195_set_delay()
361 if (plat->rmii_clk_from_mac) { in mt8195_set_delay()
364 * The egress timing can be adjusted by RMII_TXC delay macro circuit. in mt8195_set_delay()
365 * The ingress timing can be adjusted by RMII_RXC delay macro circuit. in mt8195_set_delay()
368 !!mac_delay->tx_delay); in mt8195_set_delay()
370 mac_delay->tx_delay); in mt8195_set_delay()
372 mac_delay->tx_inv); in mt8195_set_delay()
375 !!mac_delay->rx_delay); in mt8195_set_delay()
377 mac_delay->rx_delay); in mt8195_set_delay()
379 mac_delay->rx_inv); in mt8195_set_delay()
383 * the reference clk is connected to. The reference clock is a in mt8195_set_delay()
387 if (plat->rmii_rxc) { in mt8195_set_delay()
390 * by RXC delay macro circuit. in mt8195_set_delay()
393 !!mac_delay->rx_delay); in mt8195_set_delay()
395 mac_delay->rx_delay); in mt8195_set_delay()
397 mac_delay->rx_inv); in mt8195_set_delay()
401 * by TXC delay macro circuit. in mt8195_set_delay()
404 !!mac_delay->rx_delay); in mt8195_set_delay()
406 mac_delay->rx_delay); in mt8195_set_delay()
408 mac_delay->rx_inv); in mt8195_set_delay()
416 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
417 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
418 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); in mt8195_set_delay()
420 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt8195_set_delay()
421 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); in mt8195_set_delay()
422 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); in mt8195_set_delay()
426 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_delay()
427 return -EINVAL; in mt8195_set_delay()
430 regmap_update_bits(plat->peri_regmap, in mt8195_set_delay()
437 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); in mt8195_set_delay()
438 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); in mt8195_set_delay()
457 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mediatek_dwmac_config_dt()
461 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); in mediatek_dwmac_config_dt()
462 if (IS_ERR(plat->peri_regmap)) { in mediatek_dwmac_config_dt()
463 dev_err(plat->dev, "Failed to get pericfg syscon\n"); in mediatek_dwmac_config_dt()
464 return PTR_ERR(plat->peri_regmap); in mediatek_dwmac_config_dt()
467 err = of_get_phy_mode(plat->np, &plat->phy_mode); in mediatek_dwmac_config_dt()
469 dev_err(plat->dev, "not find phy-mode\n"); in mediatek_dwmac_config_dt()
473 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { in mediatek_dwmac_config_dt()
474 if (tx_delay_ps < plat->variant->tx_delay_max) { in mediatek_dwmac_config_dt()
475 mac_delay->tx_delay = tx_delay_ps; in mediatek_dwmac_config_dt()
477 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); in mediatek_dwmac_config_dt()
478 return -EINVAL; in mediatek_dwmac_config_dt()
482 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { in mediatek_dwmac_config_dt()
483 if (rx_delay_ps < plat->variant->rx_delay_max) { in mediatek_dwmac_config_dt()
484 mac_delay->rx_delay = rx_delay_ps; in mediatek_dwmac_config_dt()
486 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); in mediatek_dwmac_config_dt()
487 return -EINVAL; in mediatek_dwmac_config_dt()
491 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); in mediatek_dwmac_config_dt()
492 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); in mediatek_dwmac_config_dt()
493 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); in mediatek_dwmac_config_dt()
494 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac"); in mediatek_dwmac_config_dt()
495 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol"); in mediatek_dwmac_config_dt()
502 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clk_init()
505 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL); in mediatek_dwmac_clk_init()
506 if (!plat->clks) in mediatek_dwmac_clk_init()
507 return -ENOMEM; in mediatek_dwmac_clk_init()
509 for (i = 0; i < variant->num_clks; i++) in mediatek_dwmac_clk_init()
510 plat->clks[i].id = variant->clk_list[i]; in mediatek_dwmac_clk_init()
512 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks); in mediatek_dwmac_clk_init()
522 if (plat->rmii_clk_from_mac) { in mediatek_dwmac_clk_init()
523 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal"); in mediatek_dwmac_clk_init()
524 if (IS_ERR(plat->rmii_internal_clk)) in mediatek_dwmac_clk_init()
525 ret = PTR_ERR(plat->rmii_internal_clk); in mediatek_dwmac_clk_init()
527 plat->rmii_internal_clk = NULL; in mediatek_dwmac_clk_init()
536 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_init()
539 if (variant->dwmac_set_phy_interface) { in mediatek_dwmac_init()
540 ret = variant->dwmac_set_phy_interface(plat); in mediatek_dwmac_init()
542 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret); in mediatek_dwmac_init()
547 if (variant->dwmac_set_delay) { in mediatek_dwmac_init()
548 ret = variant->dwmac_set_delay(plat); in mediatek_dwmac_init()
550 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret); in mediatek_dwmac_init()
561 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clks_config()
565 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
567 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); in mediatek_dwmac_clks_config()
571 ret = clk_prepare_enable(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
573 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret); in mediatek_dwmac_clks_config()
577 clk_disable_unprepare(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
578 clk_bulk_disable_unprepare(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
590 plat->mac_interface = priv_plat->phy_mode; in mediatek_dwmac_common_data()
591 if (priv_plat->mac_wol) in mediatek_dwmac_common_data()
592 plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL; in mediatek_dwmac_common_data()
594 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; in mediatek_dwmac_common_data()
595 plat->riwt_off = 1; in mediatek_dwmac_common_data()
596 plat->maxmtu = ETH_DATA_LEN; in mediatek_dwmac_common_data()
597 plat->host_dma_width = priv_plat->variant->dma_bit_mask; in mediatek_dwmac_common_data()
598 plat->bsp_priv = priv_plat; in mediatek_dwmac_common_data()
599 plat->init = mediatek_dwmac_init; in mediatek_dwmac_common_data()
600 plat->clks_config = mediatek_dwmac_clks_config; in mediatek_dwmac_common_data()
602 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in mediatek_dwmac_common_data()
603 sizeof(*plat->safety_feat_cfg), in mediatek_dwmac_common_data()
605 if (!plat->safety_feat_cfg) in mediatek_dwmac_common_data()
606 return -ENOMEM; in mediatek_dwmac_common_data()
608 plat->safety_feat_cfg->tsoee = 1; in mediatek_dwmac_common_data()
609 plat->safety_feat_cfg->mrxpee = 0; in mediatek_dwmac_common_data()
610 plat->safety_feat_cfg->mestee = 1; in mediatek_dwmac_common_data()
611 plat->safety_feat_cfg->mrxee = 1; in mediatek_dwmac_common_data()
612 plat->safety_feat_cfg->mtxee = 1; in mediatek_dwmac_common_data()
613 plat->safety_feat_cfg->epsi = 0; in mediatek_dwmac_common_data()
614 plat->safety_feat_cfg->edpp = 1; in mediatek_dwmac_common_data()
615 plat->safety_feat_cfg->prtyen = 1; in mediatek_dwmac_common_data()
616 plat->safety_feat_cfg->tmouten = 1; in mediatek_dwmac_common_data()
618 for (i = 0; i < plat->tx_queues_to_use; i++) { in mediatek_dwmac_common_data()
619 /* Default TX Q0 to use TSO and rest TXQ for TBS */ in mediatek_dwmac_common_data()
621 plat->tx_queues_cfg[i].tbs_en = 1; in mediatek_dwmac_common_data()
634 priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL); in mediatek_dwmac_probe()
636 return -ENOMEM; in mediatek_dwmac_probe()
638 priv_plat->variant = of_device_get_match_data(&pdev->dev); in mediatek_dwmac_probe()
639 if (!priv_plat->variant) { in mediatek_dwmac_probe()
640 dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n"); in mediatek_dwmac_probe()
641 return -EINVAL; in mediatek_dwmac_probe()
644 priv_plat->dev = &pdev->dev; in mediatek_dwmac_probe()
645 priv_plat->np = pdev->dev.of_node; in mediatek_dwmac_probe()
670 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in mediatek_dwmac_probe()
684 struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev); in mediatek_dwmac_remove()
691 { .compatible = "mediatek,mt2712-gmac",
693 { .compatible = "mediatek,mt8195-gmac",
704 .name = "dwmac-mediatek",