Lines Matching +full:mac +full:- +full:clk +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
40 #define AVE_RXCR 0x204 /* RX Setup */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
52 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */
70 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
73 #define AVE_RXDM_SIZE_64 0x6000 /* Rx Descriptor Memory Size 24KB */
79 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
82 #define AVE_RXDM_SIZE_32 0x4000 /* Rx Descriptor Memory Size 16KB */
93 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
115 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
118 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */
131 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
132 #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */
141 #define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */
160 /* RX */
176 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */
190 #define AVE_NR_RXDESC 256 /* Rx descriptor */
209 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit)
257 struct clk *clk[AVE_MAX_CLKS]; member
278 struct ave_desc_info rx; member
303 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) in ave_desc_read()
304 + entry * priv->desc_size + offset; in ave_desc_read()
306 return readl(priv->base + addr); in ave_desc_read()
321 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) in ave_desc_write()
322 + entry * priv->desc_size + offset; in ave_desc_write()
324 writel(val, priv->base + addr); in ave_desc_write()
351 ret = readl(priv->base + AVE_GIMR); in ave_irq_disable_all()
352 writel(0, priv->base + AVE_GIMR); in ave_irq_disable_all()
361 writel(val, priv->base + AVE_GIMR); in ave_irq_restore()
368 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); in ave_irq_enable()
369 writel(bitflag, priv->base + AVE_GISR); in ave_irq_enable()
379 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); in ave_hw_write_macaddr()
380 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); in ave_hw_write_macaddr()
388 vr = readl(priv->base + AVE_VR); in ave_hw_read_version()
397 struct device *dev = ndev->dev.parent; in ave_ethtool_get_drvinfo()
399 strscpy(info->driver, dev->driver->name, sizeof(info->driver)); in ave_ethtool_get_drvinfo()
400 strscpy(info->bus_info, dev_name(dev), sizeof(info->bus_info)); in ave_ethtool_get_drvinfo()
401 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version)); in ave_ethtool_get_drvinfo()
408 return priv->msg_enable; in ave_ethtool_get_msglevel()
415 priv->msg_enable = val; in ave_ethtool_set_msglevel()
421 wol->supported = 0; in ave_ethtool_get_wol()
422 wol->wolopts = 0; in ave_ethtool_get_wol()
424 if (ndev->phydev) in ave_ethtool_get_wol()
425 phy_ethtool_get_wol(ndev->phydev, wol); in ave_ethtool_get_wol()
431 if (!ndev->phydev || in __ave_ethtool_set_wol()
432 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))) in __ave_ethtool_set_wol()
433 return -EOPNOTSUPP; in __ave_ethtool_set_wol()
435 return phy_ethtool_set_wol(ndev->phydev, wol); in __ave_ethtool_set_wol()
445 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts); in ave_ethtool_set_wol()
455 pause->autoneg = priv->pause_auto; in ave_ethtool_get_pauseparam()
456 pause->rx_pause = priv->pause_rx; in ave_ethtool_get_pauseparam()
457 pause->tx_pause = priv->pause_tx; in ave_ethtool_get_pauseparam()
464 struct phy_device *phydev = ndev->phydev; in ave_ethtool_set_pauseparam()
467 return -EINVAL; in ave_ethtool_set_pauseparam()
469 priv->pause_auto = pause->autoneg; in ave_ethtool_set_pauseparam()
470 priv->pause_rx = pause->rx_pause; in ave_ethtool_set_pauseparam()
471 priv->pause_tx = pause->tx_pause; in ave_ethtool_set_pauseparam()
473 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); in ave_ethtool_set_pauseparam()
494 struct net_device *ndev = bus->priv; in ave_mdiobus_read()
502 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); in ave_mdiobus_read()
505 mdioctl = readl(priv->base + AVE_MDIOCTR); in ave_mdiobus_read()
507 priv->base + AVE_MDIOCTR); in ave_mdiobus_read()
509 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, in ave_mdiobus_read()
517 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); in ave_mdiobus_read()
523 struct net_device *ndev = bus->priv; in ave_mdiobus_write()
531 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); in ave_mdiobus_write()
534 writel(val, priv->base + AVE_MDIOWDR); in ave_mdiobus_write()
537 mdioctl = readl(priv->base + AVE_MDIOCTR); in ave_mdiobus_write()
539 priv->base + AVE_MDIOCTR); in ave_mdiobus_write()
541 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, in ave_mdiobus_write()
556 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir); in ave_dma_map()
557 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr))) in ave_dma_map()
558 return -ENOMEM; in ave_dma_map()
560 desc->skbs_dma = map_addr; in ave_dma_map()
561 desc->skbs_dmalen = len; in ave_dma_map()
570 if (!desc->skbs_dma) in ave_dma_unmap()
573 dma_unmap_single(ndev->dev.parent, in ave_dma_unmap()
574 desc->skbs_dma, desc->skbs_dmalen, dir); in ave_dma_unmap()
575 desc->skbs_dma = 0; in ave_dma_unmap()
578 /* Prepare Rx descriptor and memory */
586 skb = priv->rx.desc[entry].skbs; in ave_rxdesc_prepare()
590 netdev_err(ndev, "can't allocate skb for Rx\n"); in ave_rxdesc_prepare()
591 return -ENOMEM; in ave_rxdesc_prepare()
593 skb->data += AVE_FRAME_HEADROOM; in ave_rxdesc_prepare()
594 skb->tail += AVE_FRAME_HEADROOM; in ave_rxdesc_prepare()
601 /* map Rx buffer in ave_rxdesc_prepare()
602 * Rx buffer set to the Rx descriptor has two restrictions: in ave_rxdesc_prepare()
603 * - Rx buffer address is 4 byte aligned. in ave_rxdesc_prepare()
604 * - Rx buffer begins with 2 byte headroom, and data will be put from in ave_rxdesc_prepare()
610 ret = ave_dma_map(ndev, &priv->rx.desc[entry], in ave_rxdesc_prepare()
611 skb->data - AVE_FRAME_HEADROOM, in ave_rxdesc_prepare()
615 netdev_err(ndev, "can't map skb for Rx\n"); in ave_rxdesc_prepare()
619 priv->rx.desc[entry].skbs = skb; in ave_rxdesc_prepare()
640 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); in ave_desc_switch()
644 writel(0, priv->base + AVE_DESCC); in ave_desc_switch()
645 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, in ave_desc_switch()
648 ret = -EBUSY; in ave_desc_switch()
653 val = readl(priv->base + AVE_DESCC); in ave_desc_switch()
656 writel(val, priv->base + AVE_DESCC); in ave_desc_switch()
657 if (readl_poll_timeout(priv->base + AVE_DESCC, val, in ave_desc_switch()
661 ret = -EBUSY; in ave_desc_switch()
666 val = readl(priv->base + AVE_DESCC); in ave_desc_switch()
669 writel(val, priv->base + AVE_DESCC); in ave_desc_switch()
673 ret = -EINVAL; in ave_desc_switch()
688 proc_idx = priv->tx.proc_idx; in ave_tx_complete()
689 done_idx = priv->tx.done_idx; in ave_tx_complete()
690 ndesc = priv->tx.ndesc; in ave_tx_complete()
692 /* free pre-stored skb from done_idx to proc_idx */ in ave_tx_complete()
709 priv->stats_tx.errors++; in ave_tx_complete()
711 priv->stats_tx.collisions++; in ave_tx_complete()
716 if (priv->tx.desc[done_idx].skbs) { in ave_tx_complete()
717 ave_dma_unmap(ndev, &priv->tx.desc[done_idx], in ave_tx_complete()
719 dev_consume_skb_any(priv->tx.desc[done_idx].skbs); in ave_tx_complete()
720 priv->tx.desc[done_idx].skbs = NULL; in ave_tx_complete()
726 priv->tx.done_idx = done_idx; in ave_tx_complete()
729 u64_stats_update_begin(&priv->stats_tx.syncp); in ave_tx_complete()
730 priv->stats_tx.packets += tx_packets; in ave_tx_complete()
731 priv->stats_tx.bytes += tx_bytes; in ave_tx_complete()
732 u64_stats_update_end(&priv->stats_tx.syncp); in ave_tx_complete()
752 proc_idx = priv->rx.proc_idx; in ave_rx_receive()
753 done_idx = priv->rx.done_idx; in ave_rx_receive()
754 ndesc = priv->rx.ndesc; in ave_rx_receive()
755 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc; in ave_rx_receive()
759 if (--restpkt < 0) in ave_rx_receive()
764 /* do nothing if owner is HW (==0 for Rx) */ in ave_rx_receive()
769 priv->stats_rx.errors++; in ave_rx_receive()
776 /* get skbuff for rx */ in ave_rx_receive()
777 skb = priv->rx.desc[proc_idx].skbs; in ave_rx_receive()
778 priv->rx.desc[proc_idx].skbs = NULL; in ave_rx_receive()
780 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE); in ave_rx_receive()
782 skb->dev = ndev; in ave_rx_receive()
784 skb->protocol = eth_type_trans(skb, ndev); in ave_rx_receive()
787 skb->ip_summed = CHECKSUM_UNNECESSARY; in ave_rx_receive()
797 priv->rx.proc_idx = proc_idx; in ave_rx_receive()
800 u64_stats_update_begin(&priv->stats_rx.syncp); in ave_rx_receive()
801 priv->stats_rx.packets += rx_packets; in ave_rx_receive()
802 priv->stats_rx.bytes += rx_bytes; in ave_rx_receive()
803 u64_stats_update_end(&priv->stats_rx.syncp); in ave_rx_receive()
805 /* refill the Rx buffers */ in ave_rx_receive()
812 priv->rx.done_idx = done_idx; in ave_rx_receive()
824 ndev = priv->ndev; in ave_napi_poll_rx()
830 /* enable Rx interrupt when NAPI finishes */ in ave_napi_poll_rx()
844 ndev = priv->ndev; in ave_napi_poll_tx()
862 if (!phy_interface_mode_is_rgmii(priv->phy_mode)) in ave_global_reset()
864 writel(val, priv->base + AVE_CFGR); in ave_global_reset()
867 val = readl(priv->base + AVE_RSTCTRL); in ave_global_reset()
869 writel(val, priv->base + AVE_RSTCTRL); in ave_global_reset()
872 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); in ave_global_reset()
876 writel(AVE_GRR_GRST, priv->base + AVE_GRR); in ave_global_reset()
880 writel(0, priv->base + AVE_GRR); in ave_global_reset()
884 val = readl(priv->base + AVE_RSTCTRL); in ave_global_reset()
886 writel(val, priv->base + AVE_RSTCTRL); in ave_global_reset()
896 /* save and disable MAC receive op */ in ave_rxfifo_reset()
897 rxcr_org = readl(priv->base + AVE_RXCR); in ave_rxfifo_reset()
898 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); in ave_rxfifo_reset()
900 /* suspend Rx descriptor */ in ave_rxfifo_reset()
904 ave_rx_receive(ndev, priv->rx.ndesc); in ave_rxfifo_reset()
907 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); in ave_rxfifo_reset()
911 writel(0, priv->base + AVE_GRR); in ave_rxfifo_reset()
915 writel(AVE_GI_RXOVF, priv->base + AVE_GISR); in ave_rxfifo_reset()
920 /* restore MAC reccieve op */ in ave_rxfifo_reset()
921 writel(rxcr_org, priv->base + AVE_RXCR); in ave_rxfifo_reset()
933 gisr_val = readl(priv->base + AVE_GISR); in ave_irq_handler()
937 writel(AVE_GI_PHY, priv->base + AVE_GISR); in ave_irq_handler()
941 writel(AVE_GI_RXERR, priv->base + AVE_GISR); in ave_irq_handler()
951 priv->stats_rx.fifo_errors++; in ave_irq_handler()
956 /* Rx drop */ in ave_irq_handler()
958 priv->stats_rx.dropped++; in ave_irq_handler()
959 writel(AVE_GI_RXDROP, priv->base + AVE_GISR); in ave_irq_handler()
962 /* Rx interval */ in ave_irq_handler()
964 napi_schedule(&priv->napi_rx); in ave_irq_handler()
965 /* still force to disable Rx interrupt until NAPI finishes */ in ave_irq_handler()
971 napi_schedule(&priv->napi_tx); in ave_irq_handler()
988 return -EINVAL; in ave_pfsel_start()
990 val = readl(priv->base + AVE_PFEN); in ave_pfsel_start()
991 writel(val | BIT(entry), priv->base + AVE_PFEN); in ave_pfsel_start()
1002 return -EINVAL; in ave_pfsel_stop()
1004 val = readl(priv->base + AVE_PFEN); in ave_pfsel_stop()
1005 writel(val & ~BIT(entry), priv->base + AVE_PFEN); in ave_pfsel_stop()
1018 return -EINVAL; in ave_pfsel_set_macaddr()
1020 return -EINVAL; in ave_pfsel_set_macaddr()
1024 /* set MAC address for the filter */ in ave_pfsel_set_macaddr()
1030 priv->base + AVE_PFMBYTE(entry)); in ave_pfsel_set_macaddr()
1031 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); in ave_pfsel_set_macaddr()
1034 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); in ave_pfsel_set_macaddr()
1037 writel(0, priv->base + AVE_PFSEL(entry)); in ave_pfsel_set_macaddr()
1056 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); in ave_pfsel_set_promisc()
1057 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); in ave_pfsel_set_promisc()
1060 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); in ave_pfsel_set_promisc()
1063 writel(rxring, priv->base + AVE_PFSEL(entry)); in ave_pfsel_set_promisc()
1082 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); in ave_pfsel_init()
1091 struct phy_device *phydev = ndev->phydev; in ave_phy_adjust_link()
1097 val = readl(priv->base + AVE_TXCR); in ave_phy_adjust_link()
1100 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) in ave_phy_adjust_link()
1102 else if (phydev->speed == SPEED_100) in ave_phy_adjust_link()
1105 writel(val, priv->base + AVE_TXCR); in ave_phy_adjust_link()
1109 val = readl(priv->base + AVE_LINKSEL); in ave_phy_adjust_link()
1110 if (phydev->speed == SPEED_10) in ave_phy_adjust_link()
1114 writel(val, priv->base + AVE_LINKSEL); in ave_phy_adjust_link()
1118 rxcr = readl(priv->base + AVE_RXCR); in ave_phy_adjust_link()
1119 txcr = readl(priv->base + AVE_TXCR); in ave_phy_adjust_link()
1122 if (phydev->duplex) { in ave_phy_adjust_link()
1125 if (phydev->pause) in ave_phy_adjust_link()
1127 if (phydev->asym_pause) in ave_phy_adjust_link()
1130 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); in ave_phy_adjust_link()
1147 /* disable Rx mac */ in ave_phy_adjust_link()
1148 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); in ave_phy_adjust_link()
1149 /* change and enable TX/Rx mac */ in ave_phy_adjust_link()
1150 writel(txcr, priv->base + AVE_TXCR); in ave_phy_adjust_link()
1151 writel(rxcr, priv->base + AVE_RXCR); in ave_phy_adjust_link()
1159 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R); in ave_macaddr_init()
1162 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); in ave_macaddr_init()
1169 struct device *dev = ndev->dev.parent; in ave_init()
1170 struct device_node *np = dev->of_node; in ave_init()
1175 /* enable clk because of hw access until ndo_open */ in ave_init()
1176 for (nc = 0; nc < priv->nclks; nc++) { in ave_init()
1177 ret = clk_prepare_enable(priv->clk[nc]); in ave_init()
1184 for (nr = 0; nr < priv->nrsts; nr++) { in ave_init()
1185 ret = reset_control_deassert(priv->rst[nr]); in ave_init()
1192 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, in ave_init()
1193 priv->pinmode_mask, priv->pinmode_val); in ave_init()
1202 ret = -EINVAL; in ave_init()
1205 ret = of_mdiobus_register(priv->mdio, mdio_np); in ave_init()
1215 ret = -ENODEV; in ave_init()
1219 priv->phydev = phydev; in ave_init()
1222 device_set_wakeup_capable(&ndev->dev, !!wol.supported); in ave_init()
1233 phydev->mac_managed_pm = true; in ave_init()
1240 mdiobus_unregister(priv->mdio); in ave_init()
1242 while (--nr >= 0) in ave_init()
1243 reset_control_assert(priv->rst[nr]); in ave_init()
1245 while (--nc >= 0) in ave_init()
1246 clk_disable_unprepare(priv->clk[nc]); in ave_init()
1256 phy_disconnect(priv->phydev); in ave_uninit()
1257 mdiobus_unregister(priv->mdio); in ave_uninit()
1259 /* disable clk because of hw access after ndo_stop */ in ave_uninit()
1260 for (i = 0; i < priv->nrsts; i++) in ave_uninit()
1261 reset_control_assert(priv->rst[i]); in ave_uninit()
1262 for (i = 0; i < priv->nclks; i++) in ave_uninit()
1263 clk_disable_unprepare(priv->clk[i]); in ave_uninit()
1273 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name, in ave_open()
1278 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc), in ave_open()
1280 if (!priv->tx.desc) { in ave_open()
1281 ret = -ENOMEM; in ave_open()
1285 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc), in ave_open()
1287 if (!priv->rx.desc) { in ave_open()
1288 kfree(priv->tx.desc); in ave_open()
1289 ret = -ENOMEM; in ave_open()
1294 priv->tx.proc_idx = 0; in ave_open()
1295 priv->tx.done_idx = 0; in ave_open()
1296 for (entry = 0; entry < priv->tx.ndesc; entry++) { in ave_open()
1301 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE), in ave_open()
1302 priv->base + AVE_TXDC); in ave_open()
1304 /* initialize Rx work and descriptor */ in ave_open()
1305 priv->rx.proc_idx = 0; in ave_open()
1306 priv->rx.done_idx = 0; in ave_open()
1307 for (entry = 0; entry < priv->rx.ndesc; entry++) { in ave_open()
1312 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE), in ave_open()
1313 priv->base + AVE_RXDC0); in ave_open()
1320 /* set Rx configuration */ in ave_open()
1324 writel(val, priv->base + AVE_RXCR); in ave_open()
1328 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); in ave_open()
1331 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; in ave_open()
1333 writel(val, priv->base + AVE_IIRQC); in ave_open()
1338 napi_enable(&priv->napi_rx); in ave_open()
1339 napi_enable(&priv->napi_tx); in ave_open()
1341 phy_start(ndev->phydev); in ave_open()
1342 phy_start_aneg(ndev->phydev); in ave_open()
1348 disable_irq(priv->irq); in ave_open()
1349 free_irq(priv->irq, ndev); in ave_open()
1360 disable_irq(priv->irq); in ave_stop()
1361 free_irq(priv->irq, ndev); in ave_stop()
1364 phy_stop(ndev->phydev); in ave_stop()
1365 napi_disable(&priv->napi_tx); in ave_stop()
1366 napi_disable(&priv->napi_rx); in ave_stop()
1371 for (entry = 0; entry < priv->tx.ndesc; entry++) { in ave_stop()
1372 if (!priv->tx.desc[entry].skbs) in ave_stop()
1375 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE); in ave_stop()
1376 dev_kfree_skb_any(priv->tx.desc[entry].skbs); in ave_stop()
1377 priv->tx.desc[entry].skbs = NULL; in ave_stop()
1379 priv->tx.proc_idx = 0; in ave_stop()
1380 priv->tx.done_idx = 0; in ave_stop()
1382 /* free Rx buffer */ in ave_stop()
1383 for (entry = 0; entry < priv->rx.ndesc; entry++) { in ave_stop()
1384 if (!priv->rx.desc[entry].skbs) in ave_stop()
1387 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE); in ave_stop()
1388 dev_kfree_skb_any(priv->rx.desc[entry].skbs); in ave_stop()
1389 priv->rx.desc[entry].skbs = NULL; in ave_stop()
1391 priv->rx.proc_idx = 0; in ave_stop()
1392 priv->rx.done_idx = 0; in ave_stop()
1394 kfree(priv->tx.desc); in ave_stop()
1395 kfree(priv->rx.desc); in ave_stop()
1407 proc_idx = priv->tx.proc_idx; in ave_start_xmit()
1408 done_idx = priv->tx.done_idx; in ave_start_xmit()
1409 ndesc = priv->tx.ndesc; in ave_start_xmit()
1410 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc; in ave_start_xmit()
1420 priv->stats_tx.dropped++; in ave_start_xmit()
1427 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx], in ave_start_xmit()
1428 skb->data, skb->len, DMA_TO_DEVICE, &paddr); in ave_start_xmit()
1431 priv->stats_tx.dropped++; in ave_start_xmit()
1435 priv->tx.desc[proc_idx].skbs = skb; in ave_start_xmit()
1440 (skb->len & AVE_STS_PKTLEN_TX_MASK); in ave_start_xmit()
1447 if (skb->ip_summed == CHECKSUM_NONE || in ave_start_xmit()
1448 skb->ip_summed == CHECKSUM_UNNECESSARY) in ave_start_xmit()
1453 priv->tx.proc_idx = (proc_idx + 1) % ndesc; in ave_start_xmit()
1460 return phy_mii_ioctl(ndev->phydev, ifr, cmd); in ave_ioctl()
1473 /* MAC addr filter enable for promiscious mode */ in ave_set_rx_mode()
1475 val = readl(priv->base + AVE_RXCR); in ave_set_rx_mode()
1476 if (ndev->flags & IFF_PROMISC || !mc_cnt) in ave_set_rx_mode()
1480 writel(val, priv->base + AVE_RXCR); in ave_set_rx_mode()
1483 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) { in ave_set_rx_mode()
1499 hw_adr->addr, 6); in ave_set_rx_mode()
1512 start = u64_stats_fetch_begin(&priv->stats_rx.syncp); in ave_get_stats64()
1513 stats->rx_packets = priv->stats_rx.packets; in ave_get_stats64()
1514 stats->rx_bytes = priv->stats_rx.bytes; in ave_get_stats64()
1515 } while (u64_stats_fetch_retry(&priv->stats_rx.syncp, start)); in ave_get_stats64()
1518 start = u64_stats_fetch_begin(&priv->stats_tx.syncp); in ave_get_stats64()
1519 stats->tx_packets = priv->stats_tx.packets; in ave_get_stats64()
1520 stats->tx_bytes = priv->stats_tx.bytes; in ave_get_stats64()
1521 } while (u64_stats_fetch_retry(&priv->stats_tx.syncp, start)); in ave_get_stats64()
1523 stats->rx_errors = priv->stats_rx.errors; in ave_get_stats64()
1524 stats->tx_errors = priv->stats_tx.errors; in ave_get_stats64()
1525 stats->rx_dropped = priv->stats_rx.dropped; in ave_get_stats64()
1526 stats->tx_dropped = priv->stats_tx.dropped; in ave_get_stats64()
1527 stats->rx_fifo_errors = priv->stats_rx.fifo_errors; in ave_get_stats64()
1528 stats->collisions = priv->stats_tx.collisions; in ave_get_stats64()
1558 struct device *dev = &pdev->dev; in ave_probe()
1573 return -EINVAL; in ave_probe()
1575 np = dev->of_node; in ave_probe()
1578 dev_err(dev, "phy-mode not found\n"); in ave_probe()
1593 return -ENOMEM; in ave_probe()
1596 ndev->netdev_ops = &ave_netdev_ops; in ave_probe()
1597 ndev->ethtool_ops = &ave_ethtool_ops; in ave_probe()
1600 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); in ave_probe()
1601 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); in ave_probe()
1603 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); in ave_probe()
1607 /* if the mac address is invalid, use random mac address */ in ave_probe()
1609 dev_warn(dev, "Using random MAC address: %pM\n", in ave_probe()
1610 ndev->dev_addr); in ave_probe()
1614 priv->base = base; in ave_probe()
1615 priv->irq = irq; in ave_probe()
1616 priv->ndev = ndev; in ave_probe()
1617 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE); in ave_probe()
1618 priv->phy_mode = phy_mode; in ave_probe()
1619 priv->data = data; in ave_probe()
1622 priv->desc_size = AVE_DESC_SIZE_64; in ave_probe()
1623 priv->tx.daddr = AVE_TXDM_64; in ave_probe()
1624 priv->rx.daddr = AVE_RXDM_64; in ave_probe()
1627 priv->desc_size = AVE_DESC_SIZE_32; in ave_probe()
1628 priv->tx.daddr = AVE_TXDM_32; in ave_probe()
1629 priv->rx.daddr = AVE_RXDM_32; in ave_probe()
1636 priv->tx.ndesc = AVE_NR_TXDESC; in ave_probe()
1637 priv->rx.ndesc = AVE_NR_RXDESC; in ave_probe()
1639 u64_stats_init(&priv->stats_tx.syncp); in ave_probe()
1640 u64_stats_init(&priv->stats_rx.syncp); in ave_probe()
1643 name = priv->data->clock_names[i]; in ave_probe()
1646 priv->clk[i] = devm_clk_get(dev, name); in ave_probe()
1647 if (IS_ERR(priv->clk[i])) in ave_probe()
1648 return PTR_ERR(priv->clk[i]); in ave_probe()
1649 priv->nclks++; in ave_probe()
1653 name = priv->data->reset_names[i]; in ave_probe()
1656 priv->rst[i] = devm_reset_control_get_shared(dev, name); in ave_probe()
1657 if (IS_ERR(priv->rst[i])) in ave_probe()
1658 return PTR_ERR(priv->rst[i]); in ave_probe()
1659 priv->nrsts++; in ave_probe()
1663 "socionext,syscon-phy-mode", in ave_probe()
1666 dev_err(dev, "can't get syscon-phy-mode property\n"); in ave_probe()
1669 priv->regmap = syscon_node_to_regmap(args.np); in ave_probe()
1671 if (IS_ERR(priv->regmap)) { in ave_probe()
1672 dev_err(dev, "can't map syscon-phy-mode\n"); in ave_probe()
1673 return PTR_ERR(priv->regmap); in ave_probe()
1675 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); in ave_probe()
1677 dev_err(dev, "invalid phy-mode setting\n"); in ave_probe()
1681 priv->mdio = devm_mdiobus_alloc(dev); in ave_probe()
1682 if (!priv->mdio) in ave_probe()
1683 return -ENOMEM; in ave_probe()
1684 priv->mdio->priv = ndev; in ave_probe()
1685 priv->mdio->parent = dev; in ave_probe()
1686 priv->mdio->read = ave_mdiobus_read; in ave_probe()
1687 priv->mdio->write = ave_mdiobus_write; in ave_probe()
1688 priv->mdio->name = "uniphier-mdio"; in ave_probe()
1689 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x", in ave_probe()
1690 pdev->name, pdev->id); in ave_probe()
1693 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx); in ave_probe()
1694 netif_napi_add_tx(ndev, &priv->napi_tx, ave_napi_poll_tx); in ave_probe()
1705 ave_id = readl(priv->base + AVE_IDR); in ave_probe()
1711 buf, priv->irq, phy_modes(phy_mode)); in ave_probe()
1716 netif_napi_del(&priv->napi_rx); in ave_probe()
1717 netif_napi_del(&priv->napi_tx); in ave_probe()
1728 netif_napi_del(&priv->napi_rx); in ave_remove()
1729 netif_napi_del(&priv->napi_tx); in ave_remove()
1746 priv->wolopts = wol.wolopts; in ave_suspend()
1760 ret = phy_init_hw(ndev->phydev); in ave_resume()
1765 wol.wolopts = priv->wolopts; in ave_resume()
1786 return -EINVAL; in ave_pro4_get_pinmode()
1788 priv->pinmode_mask = SG_ETPINMODE_RMII(0); in ave_pro4_get_pinmode()
1792 priv->pinmode_val = SG_ETPINMODE_RMII(0); in ave_pro4_get_pinmode()
1799 priv->pinmode_val = 0; in ave_pro4_get_pinmode()
1802 return -EINVAL; in ave_pro4_get_pinmode()
1812 return -EINVAL; in ave_ld11_get_pinmode()
1814 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); in ave_ld11_get_pinmode()
1818 priv->pinmode_val = 0; in ave_ld11_get_pinmode()
1821 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); in ave_ld11_get_pinmode()
1824 return -EINVAL; in ave_ld11_get_pinmode()
1834 return -EINVAL; in ave_ld20_get_pinmode()
1836 priv->pinmode_mask = SG_ETPINMODE_RMII(0); in ave_ld20_get_pinmode()
1840 priv->pinmode_val = SG_ETPINMODE_RMII(0); in ave_ld20_get_pinmode()
1846 priv->pinmode_val = 0; in ave_ld20_get_pinmode()
1849 return -EINVAL; in ave_ld20_get_pinmode()
1859 return -EINVAL; in ave_pxs3_get_pinmode()
1861 priv->pinmode_mask = SG_ETPINMODE_RMII(arg); in ave_pxs3_get_pinmode()
1865 priv->pinmode_val = SG_ETPINMODE_RMII(arg); in ave_pxs3_get_pinmode()
1871 priv->pinmode_val = 0; in ave_pxs3_get_pinmode()
1874 return -EINVAL; in ave_pxs3_get_pinmode()
1883 "gio", "ether", "ether-gb", "ether-phy",
1948 .compatible = "socionext,uniphier-pro4-ave4",
1952 .compatible = "socionext,uniphier-pxs2-ave4",
1956 .compatible = "socionext,uniphier-ld11-ave4",
1960 .compatible = "socionext,uniphier-ld20-ave4",
1964 .compatible = "socionext,uniphier-pxs3-ave4",
1968 .compatible = "socionext,uniphier-nx1-ave4",