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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21 ---------------------------------------------------------------------------*/
29 * Any 16-bit access is performed with two 8-bit accesses if the hardware
30 * can't do it directly. Most registers are 16-bit so those are mandatory.
37 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
45 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
55 #include <asm/mach-types.h>
60 #define SMC_CAN_USE_8BIT 1
61 #define SMC_CAN_USE_16BIT 1
62 #define SMC_CAN_USE_32BIT 1
63 #define SMC_NOWAIT 1
65 #define SMC_IO_SHIFT (lp->io_shift)
77 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) argument
78 #define SMC_outw(lp, v, a, r) \ argument
80 unsigned int __v = v, __smc_r = r; \
89 #define SMC_outl(v, a, r) writel(v, (a) + (r)) argument
96 #define SMC_IRQ_FLAGS (-1) /* from resource */
103 unsigned int v = val << 16; in _SMC_outw_align4() local
104 v |= readl(ioaddr + (reg & ~2)) & 0xffff; in _SMC_outw_align4()
105 writel(v, ioaddr + (reg & ~2)); in _SMC_outw_align4()
111 #define __SMC_outw(lp, v, a, r) \ argument
112 _SMC_outw_align4((v), (a), (r), \
114 (lp)->cfg.pxa_u16_align4)
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 1
121 #define SMC_CAN_USE_32BIT 1
122 #define SMC_NOWAIT 1
127 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) argument
128 #define SMC_outw(lp, v, a, r) writew(v, (a) + (r)) argument
129 #define SMC_outl(v, a, r) writel(v, (a) + (r)) argument
141 #define SMC_CAN_USE_16BIT 1
143 #define SMC_NOWAIT 1
148 while (l-- > 0) in mcf_insw()
155 while (l-- > 0) in mcf_outsw()
160 #define SMC_outw(lp, v, a, r) iowrite16be(v, (a) + (r)) argument
172 #define SMC_CAN_USE_8BIT 1
173 #define SMC_CAN_USE_16BIT 1
174 #define SMC_CAN_USE_32BIT 1
175 #define SMC_NOWAIT 1
177 #define SMC_IO_SHIFT (lp->io_shift)
182 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) argument
183 #define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r)) argument
184 #define SMC_outl(v, a, r) iowrite32(v, (a) + (r)) argument
245 /* on some platforms a u16 write must be 4-bytes aligned */
251 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
252 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
253 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
258 * always happening in irq context so no need to worry about races. TX is
262 #include <linux/dma-mapping.h>
267 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
277 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
278 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len, in smc_pxa_dma_inpump()
282 dma_async_issue_pending(lp->dma_chan); in smc_pxa_dma_inpump()
284 status = dmaengine_tx_status(lp->dma_chan, cookie, in smc_pxa_dma_inpump()
289 dmaengine_terminate_all(lp->dma_chan); in smc_pxa_dma_inpump()
291 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
301 /* fallback if no DMA available */ in smc_pxa_dma_insl()
302 if (!lp->dma_chan) { in smc_pxa_dma_insl()
311 len--; in smc_pxa_dma_insl()
317 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
318 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
321 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insl()
323 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insl()
336 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
344 /* fallback if no DMA available */ in smc_pxa_dma_insw()
345 if (!lp->dma_chan) { in smc_pxa_dma_insw()
354 len--; in smc_pxa_dma_insw()
360 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
361 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
364 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insw()
366 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insw()
460 #define TCR_ENABLE 0x0001 // When 1 we can transmit
462 #define TCR_FORCOL 0x0004 // When 1 will force a collision
463 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
464 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
465 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
466 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
467 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
468 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
469 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
525 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
526 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
527 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
549 /* BANK 1 */
550 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
551 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
553 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
556 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
561 /* BANK 1 */
562 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
566 /* BANK 1 */
567 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
568 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
569 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
573 /* BANK 1 */
574 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
578 /* BANK 1 */
579 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
580 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
581 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
582 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
583 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
584 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
593 #define MC_BUSY 1 // When 1 the last release has not completed
594 #define MC_NOP (0<<5) // No Op
595 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
630 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
632 #define PTR_READ 0x2000 // When 1 the operation is a read
686 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
700 #define CHIP_91100FD 8
710 /* 8 */ "SMC91C100FD",
741 * These phy registers are specific to our on-board phy.
744 // PHY Configuration Register 1
746 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
747 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
748 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
749 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
750 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
751 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
752 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
753 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
761 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
762 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
763 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
764 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
768 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
769 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
770 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
771 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
772 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
773 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
774 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
775 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
776 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
777 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
805 * Note: the following macros do *not* select the bank -- this must
831 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
835 * effects and use a 32-bit access.
837 * Enforce it on any 32-bit capable setup for now.
857 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
865 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
887 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
894 SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \
928 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
968 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
982 addr[0] = __v; addr[1] = __v >> 8; \
984 addr[2] = __v; addr[3] = __v >> 8; \
986 addr[4] = __v; addr[5] = __v >> 8; \
992 SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
993 SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
994 SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1000 SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1001 SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1002 SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1003 SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1036 __len -= 2; \
1037 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1040 if (SMC_CAN_USE_DATACS && lp->datacs) \
1041 __ioaddr = lp->datacs; \
1045 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1048 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1065 * Back both source (on-chip) and \
1073 __ptr -= 2; \
1078 if (SMC_CAN_USE_DATACS && lp->datacs) \
1079 __ioaddr = lp->datacs; \
1083 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \