211 #define sr32(reg)	ioread32(ioaddr + (reg))  macro
342 	rfcrSave = sr32(rfcr);  in sis635_get_mac_addr()
389 		if (sr32(mear) & EEGNT) {  in sis96x_get_mac_addr()
550 		sw32(cr, ACCESSMODE | sr32(cr));  in sis900_probe()
577 	ret = (sr32(CFGPMC) & PMESP) >> 27;  in sis900_probe()
812 #define eeprom_delay()	sr32(mear)
852 		retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);  in read_eeprom()
866 #define mdio_delay()	sr32(mear)
926 		retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);  in mdio_read()
1071 	sw32(cr, RxENA | sr32(cr));  in sis900_open()
1101 	rfcrSave = sr32(rfcr);  in sis900_init_rxfilter()
1115 			       net_dev->name, i, sr32(rfdr));  in sis900_init_rxfilter()
1153 		       net_dev->name, sr32(txdp));  in sis900_init_tx_ring()
1214 		       net_dev->name, sr32(rxdp));  in sis900_init_rx_ring()
1385 		sw32(cfg, ~EXD & sr32(cfg));  in sis900_check_mode()
1389 		sw32(cfg, EXD | sr32(cfg));  in sis900_check_mode()
1415 	if (sr32( cfg) & EDB_MASTER_EN) {  in sis900_set_mode()
1558 			net_dev->name, sr32(cr), sr32(isr));  in sis900_tx_timeout()
1636 	sw32(cr, TxENA | sr32(cr));  in sis900_start_xmit()
1689 		status = sr32(isr);  in sis900_interrupt()
1724 		       net_dev->name, sr32(isr));  in sis900_interrupt()
1886 	sw32(cr , RxENA | sr32(cr));  in sis900_rx()
1984 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_close()
2134 	pmctrl_bits = sr32(pmctrl);  in sis900_get_wol()
2162 			if (sr32(mear) & EEGNT) {  in sis900_read_eeprom()
2437 		cr_saved = sr32(cr);  in set_rx_mode()
2440 		sw32(txcfg, sr32(txcfg) | TxMLB);  in set_rx_mode()
2441 		sw32(rxcfg, sr32(rxcfg) | RxATX);  in set_rx_mode()
2467 	sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));  in sis900_reset()
2471 		status ^= sr32(isr) & status;  in sis900_reset()
2522 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_suspend()
2551 	sw32(cr, RxENA | sr32(cr));  in sis900_resume()