Lines Matching +full:tx +full:- +full:fifo +full:- +full:depth
4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
19 /* tx status vector is written over tx command header upon
32 * It consists of header, 0-3 concatination
40 u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
132 /* 001: First revision, Improved TX concatenation */
137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != dept…
139 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
140 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
144 /* RX FIFO MCL Info bits */
175 #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
177 /* 1: A TX message had the INT request bit set, the packet has been sent. */
181 #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stop…
183 #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could no…
184 #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped,…
186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
187 …NT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32…
191 #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
205 /* TX status bits */
206 #define METH_TX_ST_DONE BIT(63) /* TX complete */
208 #define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */
209 #define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */
210 #define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */
211 #define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */
212 #define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */
215 /* Tx command header bits */
216 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
222 #define PHY_QS6612X 0x0181441 /* Quality TX */
224 #define PHY_ICS1890 0x0015F42 /* ICS TX */
225 #define PHY_DP83840 0x20005C0 /* National TX */
227 #define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)