ethernet/sgi/meth.h

4 #define TX_RING_ENTRIES 64	/* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32  * It consists of header, 0-3 concatination
43 	u64		data_len:16;		/*Length of valid data in bytes-1*/
48 		u64		len:16;				/*length of buffer data - 1*/
91         u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 	char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
122 …      /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
136 …2 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != dept…
141 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
142 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
144 /* RX FIFO MCL Info bits */
149 /* RX status bits */
183 #define METH_INT_RX_UNDERFLOW	BIT(6)	/* 0: No interrupt pending, 1: FIFO was empty, packet could no…
184 #define METH_INT_RX_OVERFLOW		BIT(7)	/* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped,…
186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/		/* Bits 8 through 12 alias of RX read-pointer */
187 …H_INT_RX_RPTR_MASK 0x0000F00		/* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or…
191 #define METH_INT_TX_RPTR_MASK	0x1FF0000        /* Bits 16 through 24 alias of TX read-pointer */
203 #define METH_INT_MCAST_HASH		BIT(30) /* If RX DMA is enabled the hash select logic output is latche…
227 #define ADVANCE_RX_PTR(x)  x=(x+1)&(RX_RING_ENTRIES-1)