Lines Matching +full:firmware +full:- +full:initialised
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
126 * struct efx_special_buffer - DMA buffer entered into buffer table
133 * table entries (and so can be physically non-contiguous, although we
136 * ourselves. On later hardware this is managed by the firmware and
146 * struct efx_tx_buffer - buffer state for a TX descriptor
151 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
183 * struct efx_tx_queue - An Efx TX queue
198 * Is our index within @channel->tx_queue array.
206 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
211 * @initialised: Has hardware queue been initialised?
218 * only get the up-to-date value of @write_count if this
220 * avoid cache-line ping-pong between the xmit path and the
235 * Filled in iff @efx->type->option_descriptors; only used for PIO.
239 * only get the up-to-date value of read_count if this
241 * avoid cache-line ping-pong between the xmit path and the
255 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
273 bool initialised; member
310 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
313 * struct efx_rx_buffer - An Efx RX data buffer
339 * struct efx_rx_page_state - Page-based rx buffer state
354 * struct efx_rx_queue - An Efx RX queue
381 * @min_fill: RX descriptor minimum non-zero fill level.
431 * struct efx_channel - An Efx channel
440 * @eventq_init: Event queue initialised flag
442 * @irq: IRQ number (MSI and MSI-X only)
557 * struct efx_msi_context - Context for each MSI
572 * struct efx_channel_type - distinguishes traffic and extra channels
583 * @keep_eventq: Flag for whether event queue should be kept initialised
612 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_siena_loopback_mode)
621 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
633 /* Pseudo bit-mask flow control field */
639 * struct efx_link_state - Current state of the link
641 * @fd: Link is full-duplex
655 return left->up == right->up && left->fd == right->fd && in efx_link_state_equal()
656 left->fc == right->fc && left->speed == right->speed; in efx_link_state_equal()
660 * enum efx_phy_mode - PHY operating mode flags
681 * struct efx_hw_stat_desc - Description of a hardware statistic
684 * @dma_width: Width in bits (0 for non-DMA statistics)
685 * @offset: Offset within stats (ignored for non-DMA statistics)
696 /* Number of (single-bit) entries in a multicast filter hash */
710 * struct efx_rss_context - An RSS context for filtering
712 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
727 #define EFX_ARFS_FILTER_ID_PENDING -1
728 #define EFX_ARFS_FILTER_ID_ERROR -2
729 #define EFX_ARFS_FILTER_ID_REMOVING -3
731 * struct efx_arfs_rule - record of an ARFS filter and its IDs
733 * @spec: details of the filter (used as key for hash table). Use efx->type to
754 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
759 * @flow_id: Identifies the kernel-side flow for which this request was made
780 * struct efx_nic - an Efx NIC
798 * @vi_stride: step between per-VI registers / memory regions
813 * @extra_channel_types: Types of extra (non-traffic) channels that
846 * (valid only if channel->sync_timestamps_enabled; always negative)
853 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
858 * @selftest_work: Work item for asynchronous self-test
861 * @mcdi: Management-Controller-to-Driver Interface state
872 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
876 * @phy_data: PHY private data (including PHY-specific stats)
885 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
887 * @multicast_hash: Multicast hash table for Falcon-arch.
890 * @fc_disable: When non-zero flow control is disabled. Typically used to
896 * @loopback_selftest: Offline self-test private state
899 * @filter_state: Architecture-dependent filter table state
901 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
915 * @vf_init_count: Number of VFs that have been fully initialised.
1118 return efx->net_dev->reg_state == NETREG_REGISTERED; in efx_dev_registered()
1123 return efx->port_num; in efx_port_num()
1141 * struct efx_nic_type - Efx device type definition
1188 * The SDU length may be any value from 0 up to the protocol-
1201 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1249 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1260 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1264 * @print_additional_fwver: Dump NIC-specific additional FW version info
1272 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1472 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels); in efx_get_channel()
1473 return efx->channel[index]; in efx_get_channel()
1478 for (_channel = (_efx)->channel[0]; \
1480 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1481 (_efx)->channel[_channel->channel + 1] : NULL)
1485 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1487 _channel = _channel->channel ? \
1488 (_efx)->channel[_channel->channel - 1] : NULL)
1493 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels); in efx_get_tx_channel()
1494 return efx->channel[efx->tx_channel_offset + index]; in efx_get_tx_channel()
1500 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels); in efx_get_xdp_channel()
1501 return efx->channel[efx->xdp_channel_offset + index]; in efx_get_xdp_channel()
1506 return channel->channel - channel->efx->xdp_channel_offset < in efx_channel_is_xdp_tx()
1507 channel->efx->n_xdp_channels; in efx_channel_is_xdp_tx()
1512 return channel && channel->channel >= channel->efx->tx_channel_offset; in efx_channel_has_tx_queues()
1518 return channel->efx->xdp_tx_per_channel; in efx_channel_num_tx_queues()
1519 return channel->efx->tx_queues_per_channel; in efx_channel_num_tx_queues()
1526 return channel->tx_queue_by_type[type]; in efx_channel_get_tx_queue()
1542 for (_tx_queue = (_channel)->tx_queue; \
1543 _tx_queue < (_channel)->tx_queue + \
1549 return channel->rx_queue.core_index >= 0; in efx_channel_has_rx_queue()
1556 return &channel->rx_queue; in efx_channel_get_rx_queue()
1564 for (_rx_queue = &(_channel)->rx_queue; \
1576 return efx_rx_queue_channel(rx_queue)->channel; in efx_rx_queue_index()
1585 return &rx_queue->buffer[index]; in efx_rx_buffer()
1591 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask))) in efx_rx_buf_next()
1598 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1606 * The 10G MAC requires 8-byte alignment on the frame
1609 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1620 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; in efx_xmit_with_hwtstamp()
1624 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in efx_xmit_hwtstamp_pending()
1636 tx_queue->insert_count - tx_queue->read_count); in efx_channel_tx_fill_level()
1650 tx_queue->insert_count - tx_queue->old_read_count); in efx_channel_tx_old_fill_level()
1662 const struct net_device *net_dev = efx->net_dev; in efx_supported_features()
1664 return net_dev->features | net_dev->hw_features; in efx_supported_features()
1671 return tx_queue->insert_count & tx_queue->ptr_mask; in efx_tx_queue_get_insert_index()
1678 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)]; in __efx_tx_queue_get_insert_buffer()
1688 EFX_WARN_ON_ONCE_PARANOID(buffer->len); in efx_tx_queue_get_insert_buffer()
1689 EFX_WARN_ON_ONCE_PARANOID(buffer->flags); in efx_tx_queue_get_insert_buffer()
1690 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len); in efx_tx_queue_get_insert_buffer()